Prabeen Kumar Padhy
Hyderabad
Summary
Dynamic Senior Verification Engineer with extensive experience at Scaledge and a proven track record in PCIe Gen5 and NVMe verification. Expert in developing comprehensive test plans and achieving 100% code coverage. Skilled in debugging and functional verification, with a passion for innovative solutions and collaborative teamwork.
Overview
6
6
years of professional experience
Work History
Senior Verification Engineer
Scaledge
07.2019 - Current
Project: SiOrigin PCIe Gen5 Subsystem Verification
Client: Synopsys | Duration: Jan 2025 – Present
- Studied existing sub-system environment and prepared detailed test plans.
- Developed test cases for link-up, enumeration, speed change, and MSI interrupts.
- Wrote tests for power management features and various error scenarios.
- Debugged regression failures using waveforms/logs and fixed assertion failures.
- Achieved 100% code coverage and updated VC Formal checks.
Project: Alchip PCIe Gen5 Subsystem Verification
Client: Synopsys | Duration: Aug 2024 – Jan 2025
- Analyzed SNPS environment and PCIe protocol for subsystem understanding.
- Created DBI VIP for register access and developed functional test cases.
- Updated configuration space and adapter files as per customer specs.
Project: SoC Verification
Client: Tenafe Inc. | Duration: Sep 2021 – Aug 2024
- Developed SoC-level test cases for CPU, SB, and HMB modules.
- Reviewed code coverage, added test exclusions, and enhanced test completeness.
- Gained hands-on experience with Confluence, Bitbucket, GitHub, Jira, and Verdi
Project: AXI2OCP Bridge Testbench | Duration: Jul 2021 – Sep 2021
Designed UVM testbench architecture for AXI2OCP Bridge, implemented sequences, scoreboard, and coverage components.
Project: WDC ASE Module Verification – SSD Controller SoC Duration: Jan 2021 – Jul 2021
Enhanced ASE test plan, added checkers/testcases, closed coverage gaps, and debugged regression failures.
Project: NVMe VIP Test Suite Development | Client: Synopsys | Duration: Aug 2020 – Jan 2021
Verified NVMe features per spec v1.2b, developed comprehensive testcases and ensured 100% functional coverage.
Education
B-Tech - Electronics and Tele-Communication Engineering
Veer Surendra Sai University of Technology
Burla, Odisha06-2018
Skills
- PCIe Gen5
- NVME 12b
- System Verilog & Verilog
- Universal Verification Methodology (UVM)
- I2C
- AMBA AXI
- AMBA APB
- Code coverage
- Functional verification
- Debugging regression
- Test case development
- System verification
- Verification planning
- SoC verification
- Scripting and documentation
- Test plan creation
- C
- Synopsys VCS
- EDA
- Verdi
Accomplishments
- Received Customer Kudos Award for delivering high-quality verification solutions and exceeding client expectations on PCIe Gen5 subsystem projects.
- Honored with the Shining Star Award for consistent performance, proactive issue resolution, and strong contribution to project success.
- Recognized by leadership for exceptional debugging skills, timely delivery, and collaborative support across cross-functional teams.
Timeline
Senior Verification Engineer
Scaledge
07.2019 - Current
B-Tech - Electronics and Tele-Communication Engineering
Veer Surendra Sai University of Technology
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