Summary
Overview
Work History
Education
Skills
Accomplishments
Hobbies and Interests
Timeline
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Parnav Gupta

Kurukshetra

Summary

Dynamic Tech Lead recognized for enhancing team efficiency and consistently meeting project deadlines. Expertise in fostering collaboration through strong leadership and problem-solving skills, facilitating seamless communication across teams. Committed to leveraging advanced technology to drive strategic business goals and fuel continuous innovation.

Overview

6
6
years of professional experience

Work History

Tech Lead

STMICROELECTRONICS
Greater Noida
04.2024 - Current
  • Integrated IP blocks such as I2C and CRC into SoC architecture.
  • Responsible for IP level Synthesis for I2C & CRC.
  • Generated and integrated BIST for G3 product.
  • Performed bring-up processes on Palladium platform for emulation tasks.
  • Facilitated validation process of IP I2C within SOC verification environment.
  • Developed a script enabling automated execution of multiple test cases.

Sr. Design Engineer

STMICROELECTRONICS
Greater Noida
11.2022 - 04.2024
  • Managed delivery of SOC IP integrations including I2C, CRC, and Ethernet SS APB ports for AU1E product.
  • Responsible for the cdc and lint issues of corresponding IPs
  • Also responsible for IP level Synthesis for IPs I2C & CRC.
  • Ensured correct interrupt connectivity throughout SOC.

R&D I

SYNOPSYS
NOIDA
12.2020 - 11.2022
  • Working experience on 5nm ROM compiler having activities like Characterization of memory compiler, Margins Verification and Debug, Circuit Checks for functionality
  • BE activities:- Timing Correlation, Leakage correlation
  • Extra Activities:- Enablement of ageing flow on 5nm compilers

Intern Memory Design

SYNOPSYS
NOIDA
08.2019 - 12.2020
  • Completed Internship and gained experience of various activities like Circuit Verification, Bitcell analysis, Level Detector Analysis, Sense Amplifier Analysis, etc

Education

M.TECH - MICROELECTRONICS & VLSI DESIGN

kurukshetra University
Haryana, India
07.2019

B.TECH - ECE

Kurukshetra University
Haryana, India
07.2017

HIGHER SECONDARY -

SGMP SCHOOL
Ladwa, India
03.2013

SECONDARY -

SGMP SCHOOL
Ladwa, India
03.2011

Skills

  • RTL Coding
  • Basics of APB & AXI Protocol
  • Shell scripting
  • Basics of Logic Synthesis
  • Linux Proficiency
  • Maggilem
  • Simvision Proficiency
  • Palladium Expertise
  • Virtuoso

Accomplishments

  • Improved test run flow on Plladium by making it more informative while debugging.
  • Developed a script for automating the testcase run in SOC verification environment.
  • 2nd Position in Inter Deptt Badminton Championship in 2018.
  • 3rd Position at Inter Deptt ROSTREM in 2018.
  • Bronze medal in Wushu at distt. level in 2008.

Hobbies and Interests

  • Playing Badminton
  • Yoga
  • Bike Riding
  • Dancing

Timeline

Tech Lead

STMICROELECTRONICS
04.2024 - Current

Sr. Design Engineer

STMICROELECTRONICS
11.2022 - 04.2024

R&D I

SYNOPSYS
12.2020 - 11.2022

Intern Memory Design

SYNOPSYS
08.2019 - 12.2020

M.TECH - MICROELECTRONICS & VLSI DESIGN

kurukshetra University

B.TECH - ECE

Kurukshetra University

HIGHER SECONDARY -

SGMP SCHOOL

SECONDARY -

SGMP SCHOOL
Parnav Gupta