Experienced Physical Design Engineer in bringing forth expertise in 22nm Full Chip and 12nm Block Level PnR, STA, IR and ECO. Equipped with a diverse and promising skill-set with proficiency in Innovus , Aprisa PnR, PrimeTime, Tweaker EDA tools and C, C# languages. Able to effectively self-manage during independent projects, as well as collaborate as part of a productive team. Proven ability to lead cross-functional teams in design, development and implementation of complex projects and seeking to leverage the current technical and communication skills to effectively understand the VLSI domain and explore all of its possibilities.