Summary
Overview
Work History
Education
Skills
Languages
Accomplishments
Timeline
Generic

Pradeep Manikanta Sai Kurapati

West Godavari

Summary

Motivated and experienced RTL Designer with 4 years of experience of working in PCIe logic Protocol Analyzer, Static Timing Analysis, Clock Domain Crossing techniques, Hardware bring up and debugging.

Overview

4
4
years of professional experience

Work History

Module Lead | RTL Design Engineer

Logic Fruit Technologies Pvt Ltd
Bengaluru
2020.09 - Current

PCIe Logic Protocol Analyzer compatible up to Gen6 rate

  • Leading a team of 2 engineers, working on PCIe Gen5/Gen6 protocol Analyzer.
  • Worked on Micro Architecture and RTL design of various sub blocks of PCIe protocol Analyzer.
  • Possess comprehensive knowledge of PCIe Rx- Data link layer and ensuring precise and efficient RTL design implementations
  • Experienced in working with Xilinx Ultrascale+ and versal FPGA.
  • Experienced in working on Timing closure, CDC, synthesis and Board bring up.
  • Worked on HBM Memory, I2c, Wishbone Interface, AXI, USB (for register rd/wr).
  • Worked on Packet Decoder and Memory formatter Modules of Protocol Analyzer For PCIe traffic till Gen6 data rate
  • Managed JIRA defect tracking, ensuring timely resolutions and maintaining comprehensive RCA sheets for continuous improvement.
  • Facilitated inter-team coordination, maintained detailed design documentation, and provided clear task timelines with defined sub-tasks for streamlined project execution
  • Good knowledge in Scripting like TCL, Shell and python

Education

Bachelor of Technology - Electronics And Communications Engineering

National Institute of Technology
Surat
2020-07

Skills

  • RTL Design
  • Digital Electronics
  • PCIe
  • Static Timing Analysis
  • Clock Domain Crossing
  • VHDL
  • Verilog
  • Python
  • TCL
  • Shell scripting
  • Xilinx Vivado
  • QuestaSim
  • Chipscope Analyzer

Languages

Telugu
First Language
English
Advanced (C1)
C1
Hindi
Advanced (C1)
C1

Accomplishments

  • Selected For National Level Competition in CANSAT (mini payload satellite prototype)

Timeline

Module Lead | RTL Design Engineer

Logic Fruit Technologies Pvt Ltd
2020.09 - Current

Bachelor of Technology - Electronics And Communications Engineering

National Institute of Technology
Pradeep Manikanta Sai Kurapati