Prasad Patil

Project 1

Technology: 5nm

Name : Ci080 (INTEL)

Tool Used: Synopsys Prime time ,PC-ECO,Intel_Caliber,Fusion Compiler.

Description:- Worked on Top level model contains 2 child model and 14 hard macro, 1GHz Maximum Frequency

Responsible for handling a family level timing Closure on 60+ corners including constraints refinement and timing budgeting.

Rectangular shaped Block.

Contribution:- Challenges faced:- Due to increasing in the frequency of few clocks, critical timing registers from one module to another module with setup/hold conflict.

Worked on MCP exception constraints for changed frequency clocks , to met the timing.

Worked on the cross clock domain violation fixing based on exceptions constraints and manual eco..

Fixing the Multi bit related constraints issue , like exceptions on new mbit registers.

Fixing the family level internal and interface timing and used to give feedback on critical latency to subsystem team..

Worked on 50+ intel caliber violations related to SD and RTL. Responsible for RTL and DFT constraints/methodology checks

Written out two scripts based on requirement during the eco stage.(restrict hold buffers in o/p paths and hold buff count in critical min paths)

Project 2

Technology: 5nm

Name : Milos (INTEL)

Tool Used: Synopsys Prime time,PT-ECO,PC-ECO, Fusion Compiler,Inetl_caliber

Description:- Worked on top level module contains 2 child module and 4 instances, 1GHz Maximum Frequency

Responsible for timing analysis of Ips and family level also ECO generation from IP level

Rectangular shaped Block.

Contribution:- Challenges faced:- Fixing the interface and lane crossing timing critical paths.

Worked on constraints refinement with RTL and pnr team.

Worked with RTL and DFX team to resolved the RTL and DFX failure checks.

Worked on PT-ECO flow to fix the internal violations.

Project 1

Technology: 3nm

Name: Omega (Broadcom)

Tool Used: Synopsys - prime time, ICC2, GCA, Spyglass, PTPX prime power, tweaker, DMSA

Description:- Responsible for handling a 5 blocks sign off time closure Contains: Most critical block 605 macros, 6.62M gate counts,869MHz

Timing closure of block level and help in top level for both func and test.

Contribution:- Challenges faced: - Faced power related FSDB generation issue for Multibt signals.

Also faced crosstalk delta during the timing fixing and min/max paths.

Project 1

Technology: 5nm

Name: ADD6 (Broadcom)

Tool Used: Synopsys - prime time, ICC2, GCA, Spyglass, PTPX prime power, tweaker, DMSA

Description:- Responsible for handling 6 block from FE/RTL checks to signoff timing/power analysis

Contains: Most critical block contains 250 hard macros 5M gate counts,458MHz

Contribution: Challenges faced: - Worked on big feedthrough block, faced lots of timing critical issue, required i/o pulling.

Fixed critical reg-mem and clock gating paths using clock skewing. Also worked on MPW viol om macro

Worked closely with PD and chip level team for IO fixes.

Project 2

Technology: 7nm

Name : ADD5 (Broadcom)

Tool Used: Synopsys - prime time , ICC2 , GCA, Spyglass, PTPX prime power, tweaker, DMSA

Description:- Responsible for handling a block 3 blocks from FE/RTL checks to signoff timing/power analysis

Contains hard macros 600, 7M gate counts,704MHz

Rectangular shaped Block

Contribution: Challenges faced:- FE/RTL checks (GCA, RCA, spyglass, DCPTPX) for block

Responsible for ETM and SDF generation and validation.

Worked for block level PTPX(power) analysis and FSDB generation.

Responsible for TDRC Closure at block level and top level