Prateek Sikka
Noida
Summary
Aspiring Director/Sr. Director focused on driving strategic initiatives and creating sustainable value within semiconductor organizations.
Overview
20
20
years of professional experience
Work History
Sr. Group Manager/ MCU-MPU Architecture Lead (Microcontroller and Digital RF)
STMicroelectronics
Greater Noida
06.2022 - Current
- Leading a high performing team responsible for architecture definition for next generation SoCs in Automotive (ADAS, SW defined vehicles and body control applications).
- Working with lead customers(OEMs, Tier1) and field teams for RFIs, RFQs and high level product definition(Block Diagram, peripherals, cores, high level use-cases, KPI etc).
- Projects : 7nm 100MG zonal controller MCU with European Tier1.
- 18nm 40MG MCU for steer by wire application (US car maker). Delivering 500M$ revenue over 3 years.
- 28nm 40-80MG(SR6 Family devices) for zonal controller applications (European, Japanese car makers)
- Competition analysis, Market research and business plan formulation, roadmap definition.
- Discussion with ecosystem partners like ARM, Arteris for IP roadmap alignment.
- Working with execution teams to ensure smooth project execution overcoming implementation challenges.
- Performance exploration using platforms like VDK, PA, MATLAB etc.
- Managing an independent cost center with external contractors (Handling AUTOSAR development and maintenance activities).
- Activities include - Job requisitions, hiring, on boarding (HR), approvals and technical reviews with vendors, procurements, purchase requests and orders (in close collaboration with admin staff and procurement office).
- (Team Size – 10 Engineers globally + 16 Offsite Contractors)
SoC Architect
NXP Semiconductors
Noida
04.2021 - 05.2022
- Working on SoC architecture for automotive SoCs.
- Part of central global team working on SoCs for multiple business lines like application processor, edge processing, RADAR processors etc.
- Activities include understanding the customer requirements, performance and power exploration, use case analysis and contributing to architectural functional specifications (Including use-case descriptions, block diagrams).
- The platforms for exploration include excel calculators, data from past designs, C/C++ functional models(Like VDK), early RTL simulation and emulation models(Palladium, Zebu, Veloce).
- Working closely with systems (customer facing), IP, SoC design and verification teams for hand-offs during project inception, concept, planning and execution phases.
- Ensuring the co-relation of architectural estimation data for power and performance with pre- and post-silicon phases of the projects.
- Filing innovation disclosures, papers and patents around next generation architectural explorations.
Principal Engineer/SoC Emulation Manager
NXP Semiconductors
Noida
03.2017 - 03.2021
- Leading emulation activities for multiple projects with very successful tape-outs.
- Activities include creating Emulation requirements and plans, hand-offs between different teams, project planning and execution.
- Design bring-up, transactor integration (Like MIPI, Ethernet, DDR, Flashes, SD, eMMC etc.), model building, testbench bring-up and model releases.
- Working with dynamic targets like Lauterbach, code warrior etc. for design debug.
- Testcase creation, bring-up and waveform/debugger based debug.
- Finding design and model defects.
- Supporting global consumer space like software, application, external customer and validation teams on Emulation models(ZEBU, Veloce).
- Responsibilities also include hiring new team members, mentoring, coaching, functional and project management.
- Interfacing with internal stakeholder teams like Verification, Design, software, validation and external contacts like EDA Vendors, suppliers like services companies.
- Managing a team of 15 engineers and emulation lead for 2 projects in execution and 2 in planning.
Principal Solutions Engineer
Cadence Design Systems
Noida
10.2016 - 03.2017
- Part of a front-end team responsible for developing flows for power aware verification, UPF, power estimation for Palladium Z1.
- Working closely with validation teams, different tool R&D teams to ensure uniform behavior of power flows across all front-end tools from Cadence.
- Worked with IUS, Genus and Palladium R&D teams, marketing and product engineering teams.
Sr. Application Engineer
MathWorks India Pvt. Ltd
New Delhi
07.2015 - 10.2016
- Worked as application engineer in signal processing and communications market segment of the company.
- Worked closely with customers in aerospace, defence, semiconductors and education segments.
- Specializing in HDL coder and HDL verifier product lines which enable automatic HDL code generation and verification using MATLAB and Simulink.
- Worked closely with development team, customers and vendors (like Mentor, Cadence, Altera, Xilinx).
- Conducting seminars, product presentations, pre sales engagements, evaluations and deployments for Verification and Design solutions(FPGAs, Simulators, Standalone MATLAB and Simulink).
Lead Member Technical Staff
Mentor Graphics
Noida
06.2012 - 07.2015
- Customer engagement at early stage of emulation bring up.
- Evaluation at new customer sites as well as training, deployment and support activities for existing customers.
- Working on emulation ecosystem technologies and methodologies like UPF, Assertions, power estimation, DFT and gate level emulation.
- Working closely with marketing, sales and R&D teams across the globe.
- Supporting marketing teams by representing mentor products and technologies at various customer forums and platforms.
- Working closely with customers and development teams across the globe to identify the areas of enhancement for tool and technology roadmap definition.
- Key account wins over competition during successful technical presales engagements at customers like Qualcomm, LSI, ST, Marvell and Samsung.
Member of a front end SoC team (Functional team doing Architecture - GDS)
STMicroelectronics
Greater Noida
06.2006 - 06.2012
- Emulation lead for all HVD projects done in Noida (Mainly Set Top Box).
- Participated in more than 5 complex SoC projects all of which were great silicon success.
- Presilicon design and verification of RTL designs using tools like Synopsys design compiler, Cadence NCSim/Novas Verdi and its porting on emulation engines.
- Emulation platform delivery and usage support to verification/validation teams within ST for speedup/pre-silicon software validation and hence reduce time to market.
Education
PhD - Electronics Engineering (High Level Synthesis in VLSI)
Birla Institute of Technology and Science
Pilani, India01.2021
MTech - Integrated Electronics and Circuits
Indian Institute of Technology
Delhi, India01.2010
BTech - Electronics and Communication
Thapar Institute of Engineering and Technology
India01.2006
Skills
- Leadership
- Problem solving
- Technical mentoring
- Organizational development
- Academic advisement
- Architectural exploration
- High-level synthesis
- FPGA prototyping
- C, C
- Perl, UNIX, Python
- VHDL, Verilog, SystemVerilog
- In-circuit testing and co-emulation
- Palladium, Veloce, Zebu
- Xilinx Vivado
- High-level synthesis tools
- MATLAB and Simulink
- HDL Coder and Verifier
- Questa and NC simulation tools
- VCS
Personal Information
- Date of Birth: 08/19/84
- Marital Status: Married
Patents
- Method of High-Level Synthesis in Integrated Circuit Design using application specific bit widths, 201911028124, India
- Method and system for emulation of multiple electronic designs in a single testbench environment., 10/162,915, U.S., 2016
- Data Analytics Based Low-Cost Fall Detection and Protection Device, 201811020681, India, 2018
- Method for enabling CPU-JTAG debugger connection or improving its performance for multi-clock designs running on FPGA or Emulation systems., 15/414,107, U.S., 2018
- Method for improving runtime performance of multi-clock designs on FPGA and Emulation Systems., 2017/0351796, U.S., 2017
- Method for improving runtime performance of multi-clock designs on FPGA and Emulation systems using iterative pipelining., 15/414,129, U.S., 2018
- Synthesizable DLL on system-on-chip., 8,451,035, U.S., 05/28/13
Journal Publications
● Sikka, Prateek High-level Synthesis Assisted, Low-Latency, Area – And Power-Optimized FPGA
implementation of MUSIC algorithm for Direction of Arrival Estimation. Science Direct Sustainable Energy
Technologies and Assessments (2023) – SCI Indexed, Impact Factor-7.632
● Sikka, Prateek Hashed Access policy based secure data transmission using SDHAK-ECC. World Scientific International Journal of Cooperative Information Systems (2022) – SCI Indexed, Impact Factor- 0.563
● Sikka, Prateek, Abhijit R Asati, Chandra Shekhar, Area, speed and power optimized implementation of a band-pass FIR filter using high-level synthesis” Springer Wireless Personal Communications. (2021) – SCI Indexed, Impact Factor 1.061
● Sikka, Prateek, Abhijit R Asati, Chandra Shekhar, " Real-time FPGA Implementation of a High-Speed and Area-Optimized Harris Corner Detection Algorithm” Elsevier Microprocessors and Microsystems. (2020) – SCI Indexed, Impact Factor 1.161
● Sikka, Prateek, Abhijit R Asati, Chandra Shekhar, “Power and Area Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications”. Springer Circuits, Systems and Signal Processing(CSSP). 2020 SCI Indexed, Impact Factor 1.681
● Sikka, Prateek, Abhijit R Asati, Chandra Shekhar, "Speed optimal FPGA implementation of Encryption Algorithms for Telecom Applications”" Elsevier Microprocessors and Microsystems. (2020) - SCI Indexed, Impact Factor 1.161
● Sikka, Prateek, Abhijit R Asati, Chandra Shekhar, "High-Level Synthesis Assisted Design and Verification Framework for Automotive Radar Processors," Elsevier Microprocessors and Microsystems. (2020) SCI Indexed, Impact Factor 1.161
● Sikka, Prateek, Abhijit R Asati and Chandra Shekhar, "High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security
applications," Springer Journal of Ambient Intelligence and Humanized Computing, 29 July, 2020.SCI Indexed, Impact Factor 4.594
● Sikka, Prateek, Abhijit R. Asati, and Chandra Shekhar. "High‐speed and area‐efficient Sobel edge detector ofield‐programmable gate array for artificial intelligence and machine learning applications." Computational Intelligence Wiley Online Library (2020). SCI Indexed, Impact Factor 1.196
Conference Presentations
● Anish Vipperla, Ranendra Biswas, Prateek Sikka “ Virtual Digital Electronics Laboratory anytime anywhere using a Python-based Digital Kit”. 2023 BITS ICON 9-11 Feb, Pilani (Best Paper)
● Jain, Rajesh, Gaurav Sharma, Marcel Achim, Ashish Mathur, Prateek Sikka” Verification Reuse strategy for RTL quality functional virtual prototypes”. 2022 DVCON India, 5-6 Sep, Bengaluru
● Sikka,Prateek, Abhijit Asati, Chandra Shekhar, “Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis”. 2020 IEEE UPCON 26 Nov., MNNIT Allahabad
● Sikka,Prateek, Abhijit Asati, Chandra Shekhar,” Low Area, High Throughput Field Programmable Gate Array Implementation of Microprocessor without Interlocked Pipeline Stages”. 2020 Springer 3rd International Conference on VLSI, Communication and Signal Processing.,9-11 Oct, MNNIT Allahabad
● Sikka Prateek, Abhijit Asati, Chandra Shekhar,” High Speed and Area Efficient Sobel Edge Detector on FPGA using application specific bit widths for intermediate nodes” ”. iCASIC, 27-28 Feb, VIT, Vellore
● Pandit, Sujay and Prateek Sikka. "Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA." 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT). IEEE, 2018
● Garg, Sasha, Niharika Agarwal, S.J. Darak, and Prateek Sikka. "Spectral coexistence of candidate waveforms and DME in air-to-ground communications: Analysis via hardware software co-design on Zynq SoC." 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC), pp. 1-6. IEEE, 2017
● Sikka, Prateek. “Innovative method for better utilization of emulation hardware/FPGA resources” 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE
● Design and implementation of a digital music synthesizer. ST-India Tech Week, 2011
Tutorials
● Invited Tutorial : Sikka, Prateek. “ Design and Verification challenges for complex SoCs”. 2019 Springer 2nd International Conference on VLSI, Communication and Signal Processing., 2019 . MNNIT Allahabad.
● Invited Tutorial : Sikka, Prateek. “FPGA prototyping for VLSI designs using High level Synthesis”. 2020 Springer 3rd International Conference on VLSI, Communication and Signal Processing., 2020 . MNNIT Allahabad
● Invited Tutorial : Sikka, Prateek, Abhijit Asati, Chandra Shekhar ” Novel methods for Area, Speed and Power optimization using HLS for FPGA prototyping”. IEEE UPCON, 2020 MNNIT Allahabad
Extracurricular Activities
Special appreciation from STMicroelectronics for maximum number of HR referrals in 1 year (2022). Served as Guest/ Visiting faculty at multiple universities in India. Sr. Member, IEEE and active member of IEEE and Circuits and Systems Society since 2016. Awarded a cash reward of Rs.5000 for extraordinary trainee project work at CDIL, New Delhi. Placed in top 10% students in National Physics Olympiad at school level. Listed in Marquis Who’s Who in the world.
Hobbies and Interests
- Playing Chess
- Listening to Music and Songs
References
Available on request.
Timeline
Sr. Group Manager/ MCU-MPU Architecture Lead (Microcontroller and Digital RF)
STMicroelectronics
06.2022 - Current
SoC Architect
NXP Semiconductors
04.2021 - 05.2022
Principal Engineer/SoC Emulation Manager
NXP Semiconductors
03.2017 - 03.2021
Principal Solutions Engineer
Cadence Design Systems
10.2016 - 03.2017
Sr. Application Engineer
MathWorks India Pvt. Ltd
07.2015 - 10.2016
Lead Member Technical Staff
Mentor Graphics
06.2012 - 07.2015
Member of a front end SoC team (Functional team doing Architecture - GDS)
STMicroelectronics
06.2006 - 06.2012
PhD - Electronics Engineering (High Level Synthesis in VLSI)
Birla Institute of Technology and Science
MTech - Integrated Electronics and Circuits
Indian Institute of Technology
BTech - Electronics and Communication
Thapar Institute of Engineering and Technology