PRATIK PRAKASH BHISE

Lead chip level RTL2GDSII physical design team. (3 tapeouts)

• Exposure to IO placement planning, 3rd party IP planning, package aware chip flooplanning, power grid planning.
• Hands on with digital on top , analog on top , hierarchical pd flow.
• Interfaced with design,dft,dv,evaluation, cad teams to ensure smooth cross functional flow.
• Planned input collaterals and timely pd handoff.
• Came up with exhaustive checklist across all PD tasks to ensure quality deliverables.
• Involved in post silicon debug activities.
• Involved in hiring and ramping up PD team from scratch.
• Partial hands on : Synthesis, Formal Verification, Low power verification.
• Complete hands on: Fp, PnR, IR analysis, STA, PV
• Hands on knowledge of 65nm, 40nm, 22nm processes.

4 successful tape outs at high performance IP group delivering vector processors and subsystems to next gen modems.

• 4 M gate count including sub-blocks with more than 65% utilization
• Macro placement for 230 memories in rectilinear floorplan with 4 power domains
• SAIF based placement methodology used to lower dynamic power
• Complete timing closure at various performance modes ranging from 0.435v to 0.850v
• Complete timing closure at more than 225 corners
• 1.25 Ghz Fmax achieved
• Vmin optimization enabled to achieve better operability at lower voltages
• Netlist2GDSII Physical Design closure at 14nm, 10nm, 7nm nodes.

Responsible for Block Level and subsystem level Netlist2GDSII closure.

• 6 successful tape outs at PMC-SIERRA and BROADCOM with complete ownership of timing and physical closure activities of 12 block level and subsystem level designs.
• Working experience at 40nm and 28 nm process nodes.
• Good understanding of physical design implementation of SERDESs, OTN processor block, PCIE PHY blocks.
• Designs with gate counts up to 10 Million, operating frequency more than 500 MHz, macro count up to 320 and average standard cell utilization up to 75%.
• MCMM optimizations and cts, constraint cleanup, custom source- synchronous interfaces, cross clock domain latency/skew balancing
• power gating implementation using header cells, In rush current analysis.
• Sta, crosstalk, noise, MPW analysis, working knowledge of process and global variation schemes, complete physical verification.
• Critical congestion and timing issues by understanding designs using data flow diagrams and interacting with RTL design teams.
• functional ECOs and LEC issues debug during ECO phase of designs.