Priti Choudhary

• Served as Verification Lead for an IoT-based SoC project, leading a cross-functional team of full-time engineers and external contractors
• Owned end-to-end verification planning, triaging & task allocation, progress tracking, ensuring smooth collaboration across distributed teams
• Brought up top-level integration tests for key host and communication peripherals including DMA, L2 cache, clock management units, memory controllers, security features, bus controllers, PDM, ADC, and PRS
• Led GLS (Gate-Level Simulation) bring-up and UPF-based power-aware verification, translating PRD (Product Requirement Document) specifications into testable power scenarios
• Verified and validated power vector configurations across multiple low-power modes and power domains, ensuring correct functionality and power intent alignment

Ethernet - Packet Parser, Forwarding Engine block verification

• Understood Ethernet protocol and packet frame formats of layer 2, layer 3 and 4 packets such as Ethernet II, SNAP-LLC, VLAN tagged frame, IPv4, IPv6, TCP-IP, UDP, RDP.
• Brought up the reference model required to verify the header extracted by the Packet Parser block in L3FE.
• Verified Parser block's feature such as Header A parsing, Header A- CPU parsing, L2/L3/L4 header extraction, Erroneous packet recognition, special packet identification etc

Encoder SoC verification

• Brought up Encoder SoC level integration tests that included clock frequency switch tests, secure -non secure check, bonding test, multiple resets test, register attribute and initial value check, encoder interrupt and connectivity check.
• Ported all the C-model based Vendor IP tests for H265, H264 , JPEG modes to SoC level UVM based environment tests.
• Added system verilog concurrent assertions, & worked to accomplish 100% line and toggle coverage for the Encoder block
• Brought up Encoder GLS level environment, and supported the design team with Encoder GLS power simulation for power analysis.

System level Register Verification

• Worked on RAL based environment, consisting of RAL scripts, Ral model files, Ral interface for Backdoor, adaptor and predictor class.
• Coded tests to verify connectivity and attribute for all the system registers including PLL , power domain register with directed tests.

• Owned AMBA 5 CHI verification for integrating coherent master CPUs with the DDR subsystem, ensuring reliable interconnect functionality.
• Developed comprehensive test plans for CHI, AXI, and QNS4 master interfaces to generate complex traffic patterns including address hazards, atomic operations, I/O-coherent snoops, and power-aware scenarios.
• Led front-end block verification of NoC and LLCC components within the DDRSS subsystem across multiple projects.
• Coded multiple interesting scenarios targeting design stage inside DDR Network On Chip IP ( NoC) , Last Level Cache Controller( LLCC) , Root Clock Gating Block.
• Achieved code and functional coverage closure for NoC and multiple master interfaces, ensuring sign-off quality verification.
• Collaborated cross-functionally with design, power-aware, LLCC, security, and DDR backend teams to align on test requirements and close key verification gaps.

• Joined as an NCG and worked on Bluetooth Low Energy (BLE) Subsystem as a verification engineer.
• Owned I/O subsystem verification that interfaces the radio block with BLE IP
• Identified and Coded tests/sequences to verify different modes of GPIO like Input/Output/Inout modes, including interrupt verification and filter logic verication
• Produced test scenarios to verify Initiator/Scanner/Advertiser filter policy, connection creation in all the different advertising channels and validating proper timing requirements