RAGHAVENDRA K
Bangalore
Summary
Result oriented and dynamic VLSI professional with 5.5 years’ experience in VLSI design verification. Strong Command on System Verilog for verification. In-depth knowledge IP verification flow, code & functional coverage, constrained random verification, assertion-based verification, UVM. Looking for competitive and challenging work environment that fully utilizes my capability. Want to contribute to the best of my ability towards the growth and development of company and to pursue a challenging career.
Overview
5
5
years of professional experience
Work History
Intel Technologies India Pvt Ltd
Bangalore
09.2022 - Current
- Verified new features of the block
- Coded the Functional Coverage at the block level
- Debugging the issues related to the block
- Supported for IP integration for SOC Verification
- Develop Scoreboard/Checkers environment for the new features
- Developed new test cases for the new features to be verified at the block level
- Working at SOC level for debug IP issues
- Hands on expertise in Verdi tool, debugging issues in verification
- Running regressions and debugging failing tests to root-cause the potential RTL bugs in the design
Juniper Networks India Pvt Ltd
Bangalore
04.2020 - 09.2022
- Block/Macro level verification begin from fully detailed test plan and test object document
- Which will help in drive and synchronize the process of verification with the team
- Creating a totally (constrained) random, re-usable block level test bench environments using System Verilog – UVM which could be re-used at full-chip, multi-chip and/or system level test benches
- Have worked on memory protection (ECC protect) tests
- Implement the the functional coverage
- Have done detailed analysis of coverage (code coverage and functional coverage) database to check missing corner case scenarios
- Once identified directed tests were implemented to cover the missing cases
- Running regressions and debugging failing tests to root-cause the potential RTL bugs in the design
- Performed gate level simulation for core blocks and SDF simulations for i/o blocks
- Develop and maintain verification plan, test plan, test list and coverage documentation
Education
Masters of Technology -
MSRIT
Bengaluru, Karnataka01.2017
Bachelor of Engineering - Electronics and Communication
NMAMIT
Nitte, Karnataka01.2015
Skills
- Design Verification
- Verilog
- System Verilog
- UVM
- Cadence NCsim
- Synopsys Verdi
- AMBA Protocols
- SPI
- OOPs concepts
- Testbenches
- Computer Architecture Basics
Languages
Kannada
First Language
English
Proficient (C2)
C2
tulu
Proficient (C2)
C2
Hindi
Upper Intermediate (B2)
B2
Telugu
Upper Intermediate (B2)
B2
Timeline
Intel Technologies India Pvt Ltd
09.2022 - Current
Juniper Networks India Pvt Ltd
04.2020 - 09.2022
Masters of Technology -
MSRIT
Bachelor of Engineering - Electronics and Communication
NMAMIT
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