Rajya Lakshmi Donkada
Staff Verification Engineer
Bangalore
Summary
Verification Engineer with extensive experience over 5+ years in SoC and Sub Systems bring-ups Simulation platforms, and Pre Silicon Verification of multiple CXL based designs. Proficient in System Verilog and UVM, with a strong foundation in Verilog and Digital Electronics
Demonstrated capability in moving from Block level to SoC level verification, and creating multiple VIP-IIP setups.
Overview
7
7
years of professional experience
Work History
Staff Verification Engineer
Synopsys
02.2024 - Current
- Creating setups for Block level or System level verification in simulation platforms
- Integrating, using and debugging the setups mainly using Synopsys VIP and Test Suite solutions
- VIP ownership for CXL. Also, supporting PCIe and System Analyzer. Started with UALink
- Helping users moving from block level to System level and then to GLS testing
- Collaborating with cross-functional teams for efficient issue resolution, resulting in improved product performance.
- Managed approximately 4 meetings, 2 cases and collateral improvement per day
- Overall worked in 10+ customer projects majorly apart from regular support
Senior Application Engineer
Synopsys
07.2023 - 02.2024
- Created internal validation setups and test plans for full validation of new verification products
Senior Application Engineer
Synopsys
07.2023 - 02.2024
- Created internal validation setups and test plans for full validation of new verification products
Applications Engineer II
Synopsys
12.2021 - 07.2023
- Developed 10+ VIP-IIP setup in two years, effectively accomplishing all client objectives and needs.
- Provided technical support to 2 clients daily on average
Applications Engineer, I
Synopsys
11.2019 - 12.2021
- Documented integration, usage and various debug aspects (around 20+ articles)
Technical Intern
Synopsys India
01.2019 - 11.2019
- Started my journey in Synopsys as a Technical Intern
- Equipped with SV, UVM technical Skills and started supporting PCIe VIP usage
- Got familiar with VCS and Verdi
- Joined Toast masters club in Delhi which helped in improving my communication skills immensely.
Embedded Systems Engineer
Sevya Multimedia
01.2018 - 09.2018
- Started working in this start up while doing fourth year of B.Tech
- Learnt advanced C topics and have done System C coding
- Learnt DPI C programming with Verilog
Education
Bachelor of Technology - Electronics And Communication
Rajiv Gandhi University of Knowledge Technologies
Pre-University Course - M.P.C.
Rajiv Gandhi University of Knowledge Technologies
High School Diploma -
Z. P. H. School
Skills
- Verilog, System Verilog and UVM
- C, Cpp, Embedded C
- Python
- Scripting
- SoC level, Block level verification
Affiliations
- Toastmasters
Personal Information
Work Preference
Work Type
Full TimeWork Location
HybridImportant To Me
Work-life balanceCareer advancementWork from home optionHobbies
- Watching movies
- Reading and Writing books
- Pulling legs ;)
Timeline
Staff Verification Engineer
Synopsys
02.2024 - Current
Senior Application Engineer
Synopsys
07.2023 - 02.2024
Senior Application Engineer
Synopsys
07.2023 - 02.2024
Applications Engineer II
Synopsys
12.2021 - 07.2023
Applications Engineer, I
Synopsys
11.2019 - 12.2021
Technical Intern
Synopsys India
01.2019 - 11.2019
Embedded Systems Engineer
Sevya Multimedia
01.2018 - 09.2018
Bachelor of Technology - Electronics And Communication
Rajiv Gandhi University of Knowledge Technologies
Pre-University Course - M.P.C.
Rajiv Gandhi University of Knowledge Technologies
High School Diploma -
Z. P. H. School
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