Summary
Overview
Work History
Education
Skills
Certification
Accomplishments
Disclaimer
Timeline
Generic
Ramakrishna Moorthy P B

Ramakrishna Moorthy P B

Pre-Silicon validation engineer
Bangalore

Summary

Experienced pre-silicon validation engineer with a 14-year track record in verifying SOC, subsystems, and IPs. Excited about contributing as a formal verification engineer or specializing in PCIE validation using SV-UVM. Committed to leveraging expertise and skills to ensure seamless functioning and reliability of complex systems. Seeking a challenging role to apply extensive knowledge and passion for verification methodologies to drive optimal results.

Overview

1826
1826
years of professional experience
4
4
Certifications

Work History

PCIe Verification / Formal Verification Engineer

Intel
Bengaluru
02.2018 - Current
  • PCIe Verification at IP level
  • Verified DLCMSM link down scenarios in Data Link Layer (Pcie IP) using SV-UVM tests
  • Formal property verification using Jasper Gold to verify a few modules in Pcie controller IP
  • Tools/Environment: System Verilog, OVM/UVM, VCS simulator, Jasper Gold
  • PCIe Verification at SOC level
  • Verified features of PCIe end-point controller at SOC level in 2 projects (one of them is 5G modem)
  • Test bench environment was in SV-UVM and test cases were in C, SV
  • Worked with Subsystem, IP, Boot-rom, SLE teams for PCIe verification
  • Reported and verified many RTL bug fixes and ECO fixes
  • Obtained several accolades during verification
  • Tools/environment: System Verilog, UVM, C, VCS simulator

Member of Technical Staff

Mirafra Technologies
Bengaluru
04.2014 - 01.2018
  • Verification of a cable modem chip (Mirafra, Client: Intel)
  • Verified RTL bug fixes and found several bugs in the design, while verifying a module called PMD (physical media dependent) in a SOC
  • Created new SV test cases and ran SOC regressions (C tests for SOC) to verify features
  • SOC level verification of a networking chip (Mirafra, Client: Broadcom)
  • Verified RTL bug fixes, which were ECO fixes in previous revision of the chip
  • Also integrated the available block level test bench environment of Watchdog timer module for running testcases at SOC level
  • CPU subsystem verification (Mirafra, Client: Qualcomm)
  • Dealt with test cases of various modules across several projects
  • While most were legacy test cases of Interrupts, Low-power modes, cache coherency, boot, pll_boost_fsm, clk and reset, DFD, some of them were developed from scratch
  • Also developed SV assertions for verification of some of the features mentioned above
  • Worked on code-coverage and functional coverage closure for Q2 & Q3 milestones
  • Also verified several ECO design fixes during my tenure and raised many RTL bugs
  • Tools/environment: System Verilog, UVM, SVA, C, VCS simulator

Product Verification Engineer (level 2)

PMC Sierra India
Bengaluru
06.2011 - 12.2013
  • Storage Rate Controller chip
  • Verification at top level, of various serial peripherals such as I2C, UART, SGPIO etc present in a subsystem called SPBC (serial peripheral bus controller)
  • All the register reads and writes required to configure the registers of these peripherals are sent to the main processor from test case using OCP sequences, which then get routed to a Global shared memory and then reach the AXI instance of SPBC
  • Block level (IP level) test bench sequences and e-verification components of SPBC such as checkers, scoreboard, monitors etc
  • Were re-used at top level
  • Coded SOC level tests and made changes in an existing top-level TB environment
  • Tools/environment: Cadence IES for simulations, Specman eRM for top level TB, vr_ad for register and memory modelling

Verification Engineer

Wipro Technologies
Bengaluru
06.201 - 06.201
  • Generic Air Interface ASIC (WIPRO, Client Nokia Seimens)
  • Coded constrained random tests in System Verilog for chip level functional verification of Uplink data path that has applications in telecommunications
  • The design is also implemented as a Matlab reference model which is used to compare the data outputted at several stages of Uplink path
  • Uplink path is a series of FIR filters which is fed with a digital file corresponding to signals such as LTE, GSM, WCDMA bundled together
  • The output of Uplink path is compared against the Matlab model output
  • Tools/environment : Synopsys VCS for simulations, SV VMM for top level TB, Matlab reference model

Intern (M.Tech Project)

Intel Technology India Pvt. Ltd.
Bengaluru
07.200 - 04.201
  • Automation of power estimation flow (Intel internship)
  • Automated the power estimation tool flow for an SOC called Mobile Internet Device using Perl scripts, during the pre-silicon validation phase of the design

Education

MTech. VLSI Design -

VIT University
Vellore
04.2001 -

B.E. - ECE

MS Ramaiah Institute of Technology
Bengaluru
04.2001 -

XII Standard -

Sri Chaitanya Junior Kalasala
Hyderabad
04.2001 -

X Standard -

Oxford Grammar High School
Hyderabad
04.2001 -

Skills

Verilog , System Verilog

Universal Verification Methodology (UVM)

C, Perl

Jasper Gold FPV

AXI 3 , APB , PCIe

Certification

Jasper Formal Fundamentals , Cadence Design Systems

Accomplishments

  • Obtained 'Performance excellence' award for my work at Qualcomm (client).
  • Obtained 'Encore feather in my cap' award for good performance at Wipro.
  • University 2nd rank holder (Silver medalist) in M.Tech (VLSI).
  • GATE 2007 (EC) score - 92 percentile.
  • 1st rank holder from 6th standard to 10th at school.

Disclaimer

I hereby declare that the information furnished above is true to the best of my knowledge.

Timeline

SystemVerilog Assertions , Cadence Design Systems

11-2024

Essential SystemVerilog for UVM , Cadence Design Systems

11-2024

Jasper Formal Fundamentals , Cadence Design Systems

10-2024

Jasper Formal Expert , Cadence Design Systems

10-2024

PCIe Verification / Formal Verification Engineer

Intel
02.2018 - Current

Member of Technical Staff

Mirafra Technologies
04.2014 - 01.2018

Product Verification Engineer (level 2)

PMC Sierra India
06.2011 - 12.2013

MTech. VLSI Design -

VIT University
04.2001 -

B.E. - ECE

MS Ramaiah Institute of Technology
04.2001 -

XII Standard -

Sri Chaitanya Junior Kalasala
04.2001 -

X Standard -

Oxford Grammar High School
04.2001 -

Verification Engineer

Wipro Technologies
06.201 - 06.201

Intern (M.Tech Project)

Intel Technology India Pvt. Ltd.
07.200 - 04.201

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Ramakrishna Moorthy P BPre-Silicon validation engineer