Rashmi Seetur
Associate Professor
Bengaluru
Summary
Hardworking and passionate job seeker with strong organizational skills eager to secure design Engineer position. Ready to help team achieve company goals. Dedicated professional with history of meeting company goals utilizing consistent and organized practices. Skilled in working under pressure and adapting to new situations and challenges to best enhance the organizational brand
Overview
17
17
years of professional experience
12
12
years of post-secondary education
3
3
Certifications
Work History
Associate Professor
PES University
8 2021 - Current
· Designed and verified a BGR with 1.8V supply and 150uW consumption, achieving +/-5% trimmed accuracy for a 0.6V reference. Under idle mode the design takes only 10% of the current to work with startup. Analyzed startup and transient response across all PVT corners and Monte Carlo simulations. Implemented 1ms startup, curvature, and level trimming. The design ensures stability greater than 65dB across the corner, the DC PSRR of -64dB and -20dB at 1MHz.
· Designed and verified a cap-less LDO. Supply of 1.8V with load current range from 30uA to 30mA and 1.4 V output. Achieved untrimmed +/-6% accuracy, with robust transient response, PSRR. line and load regulation is around 0.86mV/V and 20uA/mV. Ensured 61.2° phase margin stability across worst corner, with gain greater than 75dB. the undershoot and overshoot is 150mV and 195mV respectively. Design is verified using 28nm TSMC library.
· PMOS pass transistor based capless LDO is designed for Vin=1.8V, Vout= 1.4V, considering +/-10% supply variations, An PMOS folded cascode Error amplifier is designed which can gives maximum gain of 82dB and bandwidth of 1MHz, the stability is PM=85 degrees and VCM of 0 to 600mV, the design uses a minimum quiescent current of 5uA. The LDO is designed for the following load profile ILmin=100uA ILmax=50mA, slope of 1us it achieves a load regulation of 2.8mV/mA, and load capacitance of 1pF. To improve the load transient feed forward compensation technique is adopted.
· Designed a folded cascode topology with cascode current mirrors for high output resistance. The designed opamp working at all the corners with a worst case gain of 72dB. The design achieves Vcm range from 700mV to 1.4V with a maximum gain variations of 2dB. The total current budget of the design is up to 6uA which can work up to 1MHz band width with load capacitance of 1pF
· Designed a high-frequency, 2-stage op-amp with 30MHz bandwidth and 60° phase margin.
· Designed voltage-to-current converters for bias currents, providing 1.8V and 100uA with 1% trimmed output current accuracy for 10P and 10N, supporting multiple sinking and sourcing currents. Designed a high-frequency, 2-stage op-amp with 30MHz bandwidth and 60° phase margin. Reduced layout area by 25% using dummy capacitors and symmetrical methods.
· Design and implementation of dual band Low Noise Amplifier for IRNSS application at 1.1GHz and 2.4GHz
· Design of 2.1-2.3GHz power amplifier for Electronic warfare
· Design of accuracy configurable radix 4 adder for multimedia application
· Design of clock multiplier using VCDL
· Design of inexact 4:2 compressor for optimized Wallace tree multiplier
Associate Professor
Visveswaraya Technological University
07.2014 - 08.2021
- Designed and verified analog blocks such as single stage common source amplifier with a gain of 32dB and UGB of 2MHz with load capacitance of 10pF
- Designed and verified Current mirror circuits, cascode current mirror circuits
- Designed and verified Ramp generator circuit with a F=2MHz Vm=1V and Iq=10uA
- Designed and verified 2- stage opamp with gain of 65dB in the worst corner and PM of 65 degrees, verified Montecarlo analysis and PVT corners
- Designed Folded cascode Opamp with 80dB gain and 85 degree phase margin, current of 5uA and UGB of 1MHz
Assistant Professor
Assistant Professor
03.2007 - 02.2012
- Handled Courses such as Analog Circuit Design, Verilog HDL, Network Analysis, CMOS VLSI Design, Digital design multiple times
- Revised course objectives, course materials, instructional and assessment strategies for courses.
Education
Ph.D. - RF And Mm wave Circuit Design
VTU - Bangalore
08.2013 - 05.2019
M.Tech - VLSI And Embedded Systems
VTU - Bangalore
08.2009 - 05.2012
B E - Electronics and Communications Engineering
AIT - Chikmaglore
10.2000 - 05.2004
Skills
Transistor level analog circuit design
Creative thinking in complex environment
Design of LDO, BGR, Voltage to current converters
Intuitive and analytical understanding Ingenious approach to debug and Strong written and oral communication
Certification
Analog Circuit Design at Takshila Private Limited
Accomplishments
- Taken Internship Program on Digital VLSI Design
- Conducted workshop on 5G system level design using cadence AWR
- Two students are doing internship on designing a Low Noise Amplifier at 5GHz
Journalpublications
- Design of 2.4 GHz LNA Using Microstrip Narrow Band Pass Filter, 2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3), Srinagar Garhwal, India, 2023, 1-6, 10.1109/IC2E357697.2023.10262797
- Design of 25W S Band Power Amplifier for RADAR Applications, 2023 3rd Asian Conference on Innovation in Technology (ASIANCON), Ravet IN, India, 2023, 1-5, 10.1109/ASIANCON58793.2023.10269860
- Multi-bit Limited Magnitude Error Detection and Correction Codes for MLC Cell Memories, 2023 8th International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2023, 191-197, 10.1109/ICCES57224.2023.10192841
- Design and Implementation of Novel Reversible Full Adder using QCA, 2023 7th International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2023, 1460-1465, 10.1109/ICCMC56507.2023.10084152
- Analysis of Non-Minimum Phase Buck Boost Converters, 7th International Conference on Computer Applications in Electrical Engineering-Recent Advances (CERA), IIT Roorkee, India, October 27 - 29,2023
- Design of a 90nm Instrumentation Amplifier for High Precision Signal Acquisition Applications, 2023 International Conference on Smart Instrumentation, Measurement and Applications, Kuala Lumpur, Malaysia, 2023
- Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications, Journal of Integrated Circuits, 18, 2, September 2023, https://doi.org/10.29292/jics.v18i2.691
- Error Resilient Approximate Restoring Divider for Image Processing Application, 20th India Council International Conference (INDICON) - 2023, 14-17 December 2023
- Design and Simulation of fourth order minimum phase buck converter, International conference in Next Generation Electronics NEleX 2023, 14-16 December 2023,VIT, India
- Design of Clock Multiplier Using Modified Voltage-Controlled Delay Line, IEEE 15th International Conference on Computational Intelligence and Communication Networks (CICN), Dec 22-23, 2023 at Hotel Mandarine, Bangkok, Thailand
- A Novel Single Phase Latch-Mux Based Dual-Edge-Triggering Flip-Flop for Low Power Applications, IEEE 15th International Conference on Computational Intelligence and Communication Networks (CICN), Dec 22-23, 2023 at Hotel Mandarine, Bangkok, Thailand
- 60 GHz common gate single stage current reuse cascode LNA topology for high data rate applications, Journal of Electronic Materials, October 2020, Springer US
- Design of A 60 GHz Power Amplifier in A 45nm CMOS, International Journal of Reconfigurable and Embedded Systems, 8, 1, March 2019, 14~26, 2089-4864, 10.11591/Ijres.V8.I1.Pp1426
- Design and Implementation of Low Noise Amplifier At 60GHz using Current Mirror Feedback, International Journal of Innovative Technology and Exploring Engineering (IJITEE), 8, 9S3, July 2019
- A 60GHz High Gain CG-CG Current Reuse Low Noise Amplifier for Inter Satellite Communication for Space, International Journal of Pure and Applied Mathematics, 119, 14, 2018, 95-101, 1314-3395
- Design Of 60 GHz CMOS Power Amplifier To Improve Power Added Efficiency, IEEE conference 2017 at GAT, Bangalore
- Quantum Efficient reversible ALU, National conference NCIET held at Christ University Faculty of Engineering, Bangalore in Feb,2015
- 60GHz inductance degeneration low noise amplifier, ICCIC 2014, IEEE at Park engineering college, Coimbatore
Languages
English
Kannada
References
- Dr. Chandar S, Professor, PES University, chandarts@pes.edu, +91 81970 67914
- Sowmya K S, Senior Test Specialist, HCL Technologies Private Limited, sowmya.ks@hcl.com, +91 9980082765
Interests
Playing Badmiton
Yoga
Playing Veena
Timeline
Associate Professor
Visveswaraya Technological University
07.2014 - 08.2021
Ph.D. - RF And Mm wave Circuit Design
VTU - Bangalore
08.2013 - 05.2019
M.Tech - VLSI And Embedded Systems
VTU - Bangalore
08.2009 - 05.2012
Assistant Professor
Assistant Professor
03.2007 - 02.2012
B E - Electronics and Communications Engineering
AIT - Chikmaglore
10.2000 - 05.2004
Associate Professor
PES University
8 2021 - Current
Analog Circuit Design at Takshila Private Limited
RF and Millimeterwave Circuit Design at Coursera
Low Noise Amplifier Design at RAHSOFT
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