Revathi Ganesan

Expert in driving project completions, evidenced by successfully taping out 5 projects, and excelling in high-stakes environments by optimizing designs for peak performance. Detail-oriented, organized and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success.

• Completed Tape in of 5 projects performing various layout activities and verification
• Invited as a guest speaker on the Role of Women in AI by CMTI, Bengaluru an R&D Institution under GOI. 14th March, 2024
• Level 2 in published blog VLSI PD Essentials
• Certified Physical Design Engineer from Global University of Engineering, San Jose, CA, USA
• Certification for Completion for Creating Accessible WordPress Sites -22/3/2024
• Certification on LinkedIn for confidence, OKRs, habits for success

IEEE Student Branch, Nirma University, April21 - Mar'22

• Teamwork: Planned year-long activities for UG and PG students by coordinating with a team of 18 members
• Initiative: Conducted workshops on writing papers at IEEE conferences, Organized IEEE conference-2021 in Nirma, University

• Revathi Ganesan and GS Javed, “A novel approach of frequency-based power reduction in the die partition using UPF modelling and static power dissipation based analysis”,” Workshop on the role of Women in Science, Technology and Society, Mar. 15, 2024.

• R. Ganesan and D. Kothari, “Quantum Key Agreement simulation using pattern-based encoding,” IEEE Xplore, Feb. 01, 2022. Available: https://ieeexplore.ieee.org/document/9744215.

• R. Ganesan, “Li-Fi technology in wireless communication – Revathi Ganesan,” Yuva Engineers, 24-Jan- 2014. [Online]. Available:http://www.yuvaengineers.com/li-fi-technology-in-wireless-communication-revathi-ganesan

Intel Pvt. Ltd.

Graduate Technical Intern

May' 2021– June' 2022 Bengaluru

Project Consultation: Worked on IO blocks to optimize PnR flows in Synopsys Fusion Compiler

Process Improvement: Performed automation in MCSS scenarios which saved 60% of the turnaround time to fetch timing violations in the arcs

Development: E xperimented with the placement and routing of nets according to the constraints and placed blockages to reduce congestion area, power and timing violations

ChipEdge Pvt. Ltd. in association with Global Univ. of Engg., San Jose, CA, USA

VLSI Physical Design Engineer

Oct. 2018. – Mar 2019 Bengaluru

Project Consultation: Worked on 5 projects for RTL2GDS2 on ICC and verified timing in Primetime

Process Improvement: Automated the flows through inline command and error after each step reduced effort time significantly

Development: Built CSS, XML files for corner cases and constraints drive PnR was conducted using placement, routing blockages and critical clock net using CCD

Infosys Pvt. Ltd.

Systems Engineer Intern

May. 2015. – Oct. 2015, Mysore

Onsite Consultation: Development and maintenance of websites and software

Process Improvement: Introduced automation through Python that reduced maintenance drastically

Development: Worked on Front end GUI interface using HTML, CSS and maintained database

Harvard University (edX course)

CS50, Jul. 2020 – Aug. 2020

• Person face recognition in a photograph- Detect a person using facial recognition and identification using python and Visual Studio Code, tictactoe- using minimax algorithm computer plays with user, he wins with 20% accuracy, Knights Puzzle solved using symbol and knowledge database, Minesweeper- Computer plays with 99% accuracy

Allegro X Design Entity HDL Front-to-Back Flow vSPB23.1, Cadence Design Systems - [Aug'2024]

IEEE Professional Member