Summary
Overview
Work History
Education
Skills
Certification
Interests
Timeline
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Rishabh Kaistha

Rishabh Kaistha

DFT Engineer
House No. C-1001 JM orchid Sector-76 Noida

Summary

Staff DFT Design Engineer with around 8 years of Work Experience with ST-Microelectronics and NXP India Pvt. Ltd. in the Microcontrollers and Automotive SOC DFT teams, motivated towards research interests in semiconductor testing techniques and methodologies. Being a DFT Engineer I believe that Quality comes above all.

Overview

1825
1825
years of professional experience
4
4
Certifications

Work History

Staff Design Engineer

ST Microelectronics
Greater Noida
02.2023 - Current
  • Worked as the DFT lead for Two Microcontroller Based Projects with end to end responsibility for DFT RTL, Architecture to Silicon activities.
  • Successful Tape-out of two 40nm Multipurpose Microcontroller SOC's with high density logic and multivoltage operation.

Lead Design Engineer

Nxp India Pvt. Ltd.
Noida
06.201 - 01.202
  • Owned Test-Pin Muxing Architecture and I.P. and presented it in multiple forums across Business lines.
  • Worked on end to end on Boundary Scan implementation, verification and Tester support for Radar based 16fin-fet design.
  • Worked on RTL level DFT Integration on Multiple TAP based designs on 28nm design.
  • Working on Enabling Scan Insertion setups and flows for the 5nm design.
  • Involved in IJTAG based RTL generation and Verification flows.
  • Worked on ATPG, creating reusable setups , enabling multiple fault models - Traditional Fault models like : Stuck/Transition/iddq/SDD/Path Delay/Cell aware and worked on New emerging modelling, interconnect open/shorts.
  • Coverage analysis on SA/TD models for meeting high automotive quality targets.
  • Worked on Test-Pin Muxing implementation and Verification.
  • Involved in STA/Timing and Silicon Debugs for multiple radar based Products. One of the Silicon debug was converted into a Patent.
  • Knowledge of RTL level DFT-integration, Implementation on EDT's/ Reset and Clock Architecture.

ST Microelectronics
01.2017 - 06.2017
  • Worked on analog based ESD circuits implementation and verification.

Education

B.E - Electronics and Communication

THAPAR UNIVERSITY PATIALA

Skills

Self learning and motivation towards goal fulfilment

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Certification

Patent approved on Enhanced DFT At speed Testing by checking clocking infrastructure during scan tests.

Interests

Playing Badminton and TT in my Free time , Watching Movies and TV series, Trekking.

Timeline

Staff Design Engineer

ST Microelectronics
02.2023 - Current

ST Microelectronics
01.2017 - 06.2017

B.E - Electronics and Communication

THAPAR UNIVERSITY PATIALA

Lead Design Engineer

Nxp India Pvt. Ltd.
06.201 - 01.202

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Rishabh KaisthaDFT Engineer