Rishavnath Satapathy

• Post silicon power and perf validation on compute products. My day-to-day job is extensive power and performance profiling on internal and AMD/Intel/ARM products. Power and Perf characterization of benchmarks using DAQ and many internal tools. Firmware and kernel instrumentation and development of custom tools.
• ARB Audit, Competitive Analysis. Execute the lab exercises using Qualcomm tools and generate recommendations for internal team. Create Debug and profiling tools, Writing firmware. Automation.

Developed a manageability solution for AMD Ryzen APU, integrating a customized Cadence LX6 core.
Key Responsibilities:
Prototyping and Evaluation
1. Evaluated various CPU IPs and SW stack, RTOS(RTOS, TLS stack, TCP/IP stack, servers) for manageability application.
2. Estimated memory and MIPS requirements using Cycle-accurate SystemC simulator and profiler.
Pre-Silicon
1. Created Simulation compatible manageability stack on top of FreeRTOS.
Bring-up and Post-Silicon
1. Developed manageability solution to offload DASH NW packets to dedicated LX6 CPU.
2. Executed bring-up and post-silicon phases, ensuring successful integration.

3. Implemented MMU and TLS 1.3 for enhanced security.
Optimization
1. Optimized power, code and memory using AMD and Cadence profiling tools.

Designed and developed firmware for Athena, a Gen4 PCIe switch for cloud servers. Key responsibilities included:
1. Firmware Development: Created firmware from scratch for PCIe switch Like I2C, UART, GOIO drivers, enclosure management for NVMe/SCSI, remote management, RTOS prototyping and development.
2. Pre-Silicon Validation: Executed C/RTL co-simulation and FPGA validation.
3. Post-Silicon Validation: Functional validation of firmware and characterization.

• Port Coreboot on Intel Skylake platform.
• BIOS and Firmware Support Package development.
• Post-silicon functional validation of HAL of Chrome OS and fixing issues related to PCIe, ME etc.

Worked with a global team to deliver cellular stack and mobile chipset/SOC to customers worldwide. Key responsibilities included:
1. RPC/IPC Development: Designed, maintained, and enhanced RPC/IPC code for inter-processor communication.
2. Post-silicon validation: Functional Validation of 4G stack.

Worked with a European team to develop firmware for fire safety systems.

Baremetal and RTOS firmware developmen. Linux development. mother board development.