Sandeep Thagaram
VLSI Engineer
Bangalore
Summary
Design Engineer with 6 years of experience in RTL design. Organized and reliable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.
Overview
6
6
years of post-secondary education
Work History
Lead Design Engineer
Cadence Design Systems
Bengaluru
6 2018 - Current
- Verilog coding to design and support multiple features of memory controller.
- Experience in Lint, CDC checks, Synthesis.
- TCL and Perl Scripting to integrate files and setup automated flow.
- Projects
- Advanced Chipkill RAS feature related to Error Correction Coding.
- Multi Channel Interface of controller. Two controllers are integrated and connected to PHY. Verilog coding related to Low power interface cross scenarios.
- Worked on several roadmap projects like DDR4 RCD parity, NP2 data path Automotive, Performance monitor.
- Subsystem wrapper project which helped to instantiate controller and PHY in one single module and help in SoC integration.
- Implementation to support 4:1 data ratio and integrate DDR LPI modules for HBM3
- Established Genus physical synthesis flow which enabled controller team to analyses routing congestion and solve issues.
- Debug on different memories like DDR5, LPDDR4, LPDDR5.
Education
Bachelor of Technology - Electronics And Communication Engineering
GPREC
Kurnool 06.2011 - 05.2015
Masters in Technology - Microelectronics And VLSI
NIT CALICUT
Calicut 05.2016 - 05.2018
Skills
Verilog , VHDL , C Language
Accomplishments
Awarded with Quarterly Champ for contributions to Advanced Chipkill project.
Timeline
Masters in Technology - Microelectronics And VLSI
NIT CALICUT
05.2016 - 05.2018
Bachelor of Technology - Electronics And Communication Engineering
GPREC
06.2011 - 05.2015
Lead Design Engineer
Cadence Design Systems
6 2018 - Current
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