Kesana Nagamalleswarao

• 1.8+ years of experience in Physical designing of complex blocks using Synopsys IC Compiler & FC Compiler.
• Good knowledge on physical design tools like IC Compiler 2 & Fusion Compiler..
• Knowledge on Floor planning, Placement ,Routing, Extraction and Timing Analysis.
• Knowledge on concepts of STA, CTS,LVS, DRC and LEC.

Project 1 :

• Organization: Cerium Systems Project: Server
• Client: Intel Technologies Technology: 7nm
• Tools Used:
• Fusion Compiler • Prime Time
• Caliber • Conformal
• VC Static Shell

Role:

Netlist to GDS (Floorplan,power plan,Placement,CTS,Routing,Timing closure, Physical Verification and Eco Fixing)

Design Complexities:

The design is very highly dense and congested -tried different techniques like placement blockages around macros .

Description:

• Working on 7nm (1276.31) Intel project. R2G 7nm (intel) process Synthesis to Sign-off.
• Handled 7nm technology block from RTL to GDSll.
• Helped the team to resolve the flow and tool & Latest configs Regarding issues.
• Having Experience in cheetah flow.
• Have done the floorplan with meeting the timing and reducing the congestion and Based on the hierarchy of the macros and net connections.
• Haved worked on Multi voltage domain .
• Fixed the Drcs and lvs and violations of the block.
• Fixed the Fti cells issue and Bad tap and missing tap cells issue in Lv.
• Fixed the Shorts count In critical partitions.
• Fixed the Intel caliber violations Max Cap , Slow slope , Clock slowslope ,Big wire delay, Illegal cells,Slope out of Max charge.
• Fixed RV violations static and dynamic ir drop.
• Fixed the Vclp issues Iso_buf_state and Iso_spf_driver.
• Have run through the eco cycles Pt eco and tweaker eco for timing fixing and
• Fixed the timing in Prime time for all corners for the paths which are not resolvable through eco's critical paths.
• Done Endpoint optimization for the cells In the Apr flow..to meeting the Timing of critical paths
• Having Expertise in flows and methodology of Intel.

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