Summary
Overview
Work History
Education
Skills
Certification
Timeline
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SANTHAPURI VEERA VENKATA SAI KIRAN

Bangalore

Summary

Accomplished DFT Engineer with extensive experience at Intel Corporation, specializing in ATPG and scan insertion. Proficient in Fusion Compiler and Primetime, I excel in optimizing DFT flows and enhancing automation through TCL scripting. A collaborative problem-solver, I deliver tailored solutions that significantly improve test coverage and tool performance.

Overview

4
4
years of professional experience
1
1
Certification

Work History

DFT Design Engineer

Intel Corporation
04.2024 - Current
  • I am responsible for a tool called Scan Caliber which is a collection of rules checking for DFT timing bugs, ensuring its efficient implementation and maintenance for testing scan-based timing using Synopsys Primetime tool.
  • I have experience in supporting Fusion Compiler DFT flows for Scan Insertion,Test point and Corewrapper insertion.
  • Enhanced and maintained TCL scripts used for automation, ensuring accuracy and efficiency in DFT flows.
  • Fixed bugs and optimized scripts to streamline processes and improve overall tool performance.
  • Coordinated with multiple teams across departments to deliver custom solutions for identifying design bugs tailored to each team's specific requirements.
  • Collaborated closely with the scan architecture team to ensure compliance with scan timing rules and alignment with design specifications.
  • I have hands on experience with both Fusion Compiler and Primetime tools as part of my work at Intel.

DFT Engineer (AMTS)

DXCorr Hardware Technologies
11.2023 - 04.2024
  • Responsible for DFT flows related to scan insertion, ATPG, and compression logic.
  • Involved in On Product Clock Generator (OPCG) insertion for at-speed testing using Genus.
  • I used Cadence Genus and Modus for DFT insertion and ATPG and have experience with Tetramax and Tessent Shell.
  • Executed Genus flow for scan insertion and generated Modus flow for ATPG runs.
  • Generated On Product Clock Generator (OPCG) and integrated it into the Genus flow.
  • Proficient in JTAG 1149.1, MBIST, and Scan Insertion.
  • Certified in Scan and ATPG, MemoryBIST by Siemens Software.

DFT Engineer

Synapse Design
Bengaluru
11.2021 - 10.2023
  • Gained 2 years of experience in the DFT domain working with NVIDIA as a client, specializing in ATPG.
  • Responsible for running ATPG to generate patterns, increase coverage, and debug flow issues and DRC errors.
  • Conducted Pattern Bloat analysis and worked with Verdi to identify RTL issues affecting coverage or patterns.
  • Worked on MATS processes to generate stuck-at and transition patterns.
  • Worked on NVIDIA Next Gen GPU/CPU.
  • Played an active role in resolving scan-related issues, optimizing test coverage, and improving overall testability.

Education

B.Tech & M.Tech - Dual Degree - Electronics and Communication Engineering

National Institute of Technology
Rourkela

Skills

  • Digital Design
  • ATPG
  • Scan Insertion
  • TMAX
  • Fusion compiler
  • Primetime
  • Tessent Shell
  • Genus
  • Modus
  • Tcl scripting
  • IEEE 1500
  • IEEE 11491
  • IEEE 1687
  • SystemVerilog
  • Verilog HDL

Certification

  • Tessent Scan and ATPG - v22.16, Siemens Software, 06/01/23
  • VLSI-JTAG, Boundary Scan, and IJTAG, Udemy, 07/01/23
  • Bash Scripting and Shell Programming, Udemy, 09/01/23
  • Tessent MemoryBIST - v22.16, Siemens Software, 10/01/23

Timeline

DFT Design Engineer

Intel Corporation
04.2024 - Current

DFT Engineer (AMTS)

DXCorr Hardware Technologies
11.2023 - 04.2024

DFT Engineer

Synapse Design
11.2021 - 10.2023

B.Tech & M.Tech - Dual Degree - Electronics and Communication Engineering

National Institute of Technology

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