Summary
Overview
Work History
Education
Skills
ACADEMIC PROJECTS
Accomplishments
POSITIONS OF RESPONSIBILITY
EXTRA-CURRICULAR ACTIVITIES
Timeline
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SATISH KUMAR KARILLI

SATISH KUMAR KARILLI

Bangalore

Summary

Experienced ASIC Design Engineer with 8+ years in semiconductor design, RTL implementation, FPGA verification, and post-silicon testing. Proven track record of successfully leading complex projects and collaborating with cross-functional teams to achieve high-quality results. Proficient in utilizing advanced tools and technologies to optimize product performance and ensure reliability.

Overview

9
9
years of professional experience

Work History

Senior Staff Digital IC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2024 - Current
  • Lead the development and debugging of DDR bring-up activities on silicon, including creating Python scripts and resolving post-silicon issues.
  • Conducted detailed analysis and validation of RTL changes, ensuring functionality and design integrity.
  • Collaborated with systems and software teams to support post-silicon testing and customer requirements.

Staff Digital IC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2021 - 03.2023
  • Conducted DVT and power analysis for various design projects, ensuring timely delivery and accuracy.
  • Supported architectural exploration and documentation for multiple design aspects.
  • Provided training and technical support to new hires and team members.

Senior ASIC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2019 - 03.2021
  • Led the DVT and bring-up activities for complex SOC designs, collaborating with cross-functional teams.
  • Utilized advanced tools and methodologies for post-silicon validation and debugging.
  • Independently managed critical testing and validation tasks during challenging periods, such as the Covid lockdown.

ASIC Design Engineer

MaxLinear Technologies Pvt Ltd.
07.2016 - 03.2019
  • Conducted chip characterization, PVT testing, and FPGA verification for various design projects.
  • Developed and validated test environments, automation scripts, and register map files.
  • Collaborated with verification teams to create comprehensive test plans and debug design implementations.

Education

M.Tech - Microelectronics and VLSI Design

Indian Institute of Technology Madras
Chennai, India
01-2016

B.E - Electronics & Communication Engineering

Andhra University College of Engineering
Visakhapatnam, India
01-2012

Higher Secondary -

Narayana Junior College
Visakhapatnam, India
01-2008

Secondary Examination -

St. Mary’s Public School
Visakhapatnam, India
01-2006

Skills

  • Semiconductor design tools (Cadence Virtuoso,Tempus, Synopsys, Mentor Graphics)
  • Quality check tools Spyglass, VC spyglass
  • Programming languages (Python, Perl, MATLAB, C)
  • Simulation software (MATLAB, SPICE)
  • Synthesis tools (Xilinx ISE)
  • Testing equipment (oscilloscopes, spectrum analyzers, network analyzers)
  • Basic proficiency in UNIX environments

ACADEMIC PROJECTS

  • Cache Coherency for Multicore Processors Implemented cache coherency protocol on a ring bus for Sakthi processor using Bluespec System Verilog (BSV). Guided by Prof. V. Kamakoti, IIT Madras.
  • Digital IC Design Course Extracted MOS transistor parameters using SPICE models. Designed a low-power 4-input NAND gate and created its layout using Magic Tool.
  • CAD for VLSI Developed a 5-stage RISC-V processor using Bluespec System Verilog.
  • VLSI Design Lab Designed and implemented a Single Cycle MIPS Processor and an FIR Filter on FPGA.
  • Analog IC Design Course Designed a fully differential two-stage OPAMP using LTspice simulator.
  • Study on Basic Antennas Analyzed radiation patterns and antenna parameters using MATLAB. Guided by Prof. Mallikarjuna Rao, Andhra University.
  • Research Project Completed industrial training at DOORDARSHAN High Power Transmitter, Visakhapatnam.
  • Designed WATER LEVEL INDICATOR AND DETECTOR in the HARDWARE EXPO organized by Andhra University, Visakhapatnam

Accomplishments

  • Achieved ALL INDIA RANK 95 in GATE 2014.
  • Achieved ALL INDIA RANK 129 in GATE 2015 and ALL INDIA RANK 147 in GATE 2016.
  • Secured 300 Rank in State Level Entrance Examination EAMCET.
  • Got an EXCELLENCE AWARD in SRINIVASA RAMANUJAN Maths Talent Test conducted by A.I.M.Ed (Association for Improvement of Maths Education).
  • Won 1st prize in GIPSA talent test conducted by private schools association.

POSITIONS OF RESPONSIBILITY

  • Class Representative of M.Tech Microelectronics & VLSI design group, IIT Madras.
  • Placement Coordinator for M.Tech Microelectronics & VLSI design group, IIT Madras.
  • Teaching Assistant for C programming lab course under IITMadras Prof. Dr. Harishankar Ramachandran
  • Teaching Assistant for IELAB under IITMadras Prof. Prabakaran

EXTRA-CURRICULAR ACTIVITIES

  • Organized sports events at school, college, and university levels.
  • Bagged 2nd prize in Department Level Cricket competitions conducted by Andhra University.
  • Bagged 2nd prize in Department Level Soccer competitions conducted by Andhra University.
  • Got 2nd prize in Carom competitions held at Andhra University.

Timeline

Senior Staff Digital IC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2024 - Current

Staff Digital IC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2021 - 03.2023

Senior ASIC Design Engineer

MaxLinear Technologies Pvt Ltd.
04.2019 - 03.2021

ASIC Design Engineer

MaxLinear Technologies Pvt Ltd.
07.2016 - 03.2019

M.Tech - Microelectronics and VLSI Design

Indian Institute of Technology Madras

B.E - Electronics & Communication Engineering

Andhra University College of Engineering

Higher Secondary -

Narayana Junior College

Secondary Examination -

St. Mary’s Public School
SATISH KUMAR KARILLI