Shajahan Shaik

Intel client products:

• Here, I worked as the test lead for Intel Alder Lake (ADL), Raptor Lake (RPL), and Arrow Lake (ARL) processors.
• With a small team, I delivered scan test modules of Big Core, Atom Core, ring, graphics, and Display IPs to high-volume manufacturing test programs.
• As a scan test lead, I implemented AT Speed test Vmin measurement procedures for the Final Test Program, in close coordination with the requirements of the DFT teams.
• Designed partition-level voltage vs. Frequency characterization experiments to detect speed-limit paths or power-hungry logics.
• Developed new test structures and test methods by understanding new testability features in products.
• Independently debugged production or engineering reject devices to determine the root cause of problems in assembly, design, or test conditions, and provided solutions to improve yield and quality.
• Delivered Engineering Sample (ES), Quality Sample (QS), and Production Release Qualification (PRQ) samples, meeting critical milestones.
• Led Electrical Quality Assurance, reducing Defects Per Million (DPM) through rigorous RV2 debug activities to improve the test coverage.
• Resolved test program instability issues and performed data correlation for trend analysis and early identification of process-related defects.
• Developed many test time reduction methods, saved more than 50 seconds without compromising coverage or testing breadth.
• Diagnosed and resolved high Vmin logics to achieve system Vmins.
• Supported in building a new team at Intel Bangalore from scratch for test development and PDE training.
• Collaborated as a member of the technical hiring team to onboard five professionals.

• Trained on test modules at Intel Israel.
• Gained knowledge of high-volume test programs for the IceLake device during training at Intel Israel.
• Completed specialized training on IceLake high-volume testing modules at Intel's Israeli facility.

• Engaged with INTEL's customized tester to develop, integrate, and validate test programs for Coffee Lake processors.
• As a Scan Team PDE, I develop and deliver Scan core test modules for the CFL product on the roadmap.
• Test time reduction on scan modules for CFL 8+2 product.
• Fixing the correlation sightings units, EQA units, by debugging on CMT tester

Project 1: ATS to V93K platform test program conversion.

Converted Altera's Night Furry 5 Test Program from ATS to V93K platform.

• Converting test vectors into .bin format for v93k platform.
• Optimized testing process, cutting time from 300 to 108 seconds.
• Optimized vector memory allocation to accommodate 112M capacity.

Project 2: Ineda.

• Converted test patterns from .stil to v93k bin format.
• Developed Shmoo collection of SCAN, compressed scan, stuck-at-fault, and At-Speed tests.
• Test time reduction for the final test program.