Shardool Upadhyay
Allahabad
Summary
ASIC DV Engineer with extensive expertise in CPU verification, focusing on RISC-V and ARM architectures. Demonstrated success in leading high-quality verification projects using UVM and formal techniques. Strong analytical capabilities and effective collaboration within cross-functional teams drive successful outcomes in complex environments.
Overview
13
13
years of professional experience
Work History
Asic Engineer
Meta
Bangalore
10.2024 - Current
- Owned and drove the RISC-V-based CPU memory subsystem verification for multiple projects, from detailed test planning to final coverage sign-off.
- Lead SoC boot verification in collaboration with the Emulation and BootROM team.
- Owned SoC top-level verification for CPU-related use cases.
- Developed reusable and scalable C-based test infrastructure for CPU-SS verification.
Staff Engineer
Sifive India
07.2022 - 10.2024
- Owned complete end-to-end verification of CXL port in Risc-v core.
- Developed UVMbased unit testbench from scratch to verify Tilelink2 to CXL bridge functionality and lead project to closure with high quality.
- Working on Risc-v in-order core's vector-unit verification.
- Leading a matrix multiplication accelerator verification based on custom ISA.
- Developed a UVM-based unit testbench to verify matrix multiplication accelerator functionality.
- Worked on Risc-v core performance verification by creating micro benchmarks.
- Owned Cache's performance counters functionality verification using dynamic simulation and formal tool.
Staff Engineer
NXP Semiconductors
12.2015 - 06.2022
- Part of SoC verification team in Auto domain.
- Created a detailed verification plan for Arm based Cortex A78 core in SoC context and developed test scenarios for the same.
- Developed BFM based test environment to extract performance metrics (min/avg/max latency, avg. throughput) for all master slave pair in SoC.
- Lead coherent-interconnect's (Arteris) functional and performance verification in SoC.
- Developed a comprehensive strategy for system verification of arm coresight based debug subsystem (A53 core, M7 core, accelerated core, CTI-CTM, Trace subsystem, safety-debug) and executed the plan with excellent quality.
- Created a complete verification plan to verify 3rd party accelerator core and CNN IP in SoC context and lead verification to closure with excellent quality.
- Developed vision use-case scenarios for vision based auto-SoCs which include multiple vision-IPs.
- Worked on verification of safety timer,fast-dma and I2C IP in auto based SoCs.
Senior Verification Engineer
Samsung Research Institute Bangalore
07.2013 - 12.2015
- Contributed to multi-cluster coherency verification of the CPU-Memory subsystem by creating random coherency scenarios and quality debugs.
- Developed end-to-end coherency checkers & ordering checker for coherent interconnect
- Contributed in UVM based unit level verification of SLIMbus IP(MIPI)
Education
B.Tech. -
Moti Lal Nehru National Institute Of Technology(NIT Allahabad)
Prayagraj05.2013
Inter/10+2 -
B.B.S. Inter College
Prayagraj05.2008
10th -
B.B.S. Inter College
Prayagraj05.2006
Skills
- HDLs: Verilog, System Verilog
- Programming Languages: C
- Simulators: vcs, incisive
- Formal Verification: vcformal (APPS: FPV,FRV,FTA)
- Scripting Languages: Perl, Shell, Makeflow
Accomplishments
- Received 4 Winning starts here award in NXP.
- Received various peers appreciation award.
- Secured AIR 110 in GATE 2013.
Personal Information
Timeline
Asic Engineer
Meta
10.2024 - Current
Staff Engineer
Sifive India
07.2022 - 10.2024
Staff Engineer
NXP Semiconductors
12.2015 - 06.2022
Senior Verification Engineer
Samsung Research Institute Bangalore
07.2013 - 12.2015
B.Tech. -
Moti Lal Nehru National Institute Of Technology(NIT Allahabad)
Inter/10+2 -
B.B.S. Inter College
10th -
B.B.S. Inter College