SHASHIDHAR N
Bangalore
Summary
Power Analysis Engineer with 4 years of experience in RTL and GLS power characterization using Synopsys Prime-time PX (PTPX) and Power Artist. Strong expertise in DS-based power analysis, power debugging, clock gating optimization, VT swaps, UPF/CPC low-power validation, and automation for efficient low-power design signoff.
Overview
1
1
Certification
4
4
years of post-secondary education
5
5
years of professional experience
Work History
Senior Engineer
QUEST GLOBAL
Bangalore
05.2026 - Current
- Developed in-house RTL power analysis flows and methodologies using Joules RTL power.
- Generated, validated, and checked power-intent for subsystem-level UPF.
- Executed UPF, RTL, netlist, and activity linting across the power-analysis flow, identifying and resolving methodology and design issues.
Silicon Engineer
Tessolve
Bangalore
05.2023 - 05.2026
- Performed power estimation, roll-up, and tracking through all project phases using PTPX.
- Participated in defining power management schemes and low-power modes such as clock gating, power gating, DVFS, and voltage islands.
- Identified power optimization opportunities in RTL with Power Artist/RTL-A, contributing to enhanced PPA.
- Explored power optimization opportunities, suggested improvements, and drove PPA convergence.
- Executed power estimation, roll-up, and tracking through all project phases using PTPX, ensuring accurate power management.
- Engaged in pre-silicon and post-silicon power correlation and debugging efforts to enhance design accuracy.
Physical Design Engineer
Tessolve
Bangalore
03.2022 - 05.2023
- Implemented full-chip P&R flows using Synopsys ICC2 for 28nm designs, covering floorplanning, placement, CTS, routing, and signoff optimization.
- Worked on timing closure across multiple PVT corners, resolving setup, hold, and noise violations while meeting area and power constraints.
- Performed CTS and clock-network optimization to improve skew, latency, and overall timing performance.
- Analyzed congestion and routability issues and implemented floorplan/placement optimizations to improve design quality.
Education
B.E - Electronics and Communication
Bangalore Institute of Technology [ BIT ]
Bangalore 08.2017 - 07.2021
Skills
- Low-Power Methodology
- Logic Verification
- Physical Design
- RTL Power Estimation
- UPF
- CLP
- VCLP
- PTPX
- TCL
- Joules
- Automation
- Problem Solving
Certification
Synopsys Prime Power Foundation [ FN_25 ], Udemy complete TCL Programming
LANGUAGES
Title: Low-Power Design Engineer
Accomplishments
- PPRTL for power profiling
- Identified power-critical RTL modules early in the design flow, enabling power savings of up to 15% in final implementations.
- Optimized 3nm Low-power design
- Successfully reduced total power consumption by 20% through multi-voltage analysis, glitch rejection techniques, and implementation of advanced low-power strategies like power gating and clock gating.
Timeline
Senior Engineer
QUEST GLOBAL
05.2026 - Current
Silicon Engineer
Tessolve
05.2023 - 05.2026
Physical Design Engineer
Tessolve
03.2022 - 05.2023
B.E - Electronics and Communication
Bangalore Institute of Technology [ BIT ]
08.2017 - 07.2021