Summary
Overview
Work History
Education
Skills
Tools Used
Timeline
Generic

P.N.THIRUMALESH

Senior Staff Engineer

Summary

Objective: To leverage my current expertise in Place & Route, Synthesis and low power to solve complex design problems in Digital Chip design

Overview

19
19
years of professional experience

Work History

Senior Staff Engineer

Marvell India Pvt Ltd
09.2021 - Current
  • Currently working on a sub-system with 8 sub-blocks for 3nm project.
  • Own and deliver multiple tape-out worthy blocks to full chip team.
  • Working on Synthesis and PnR to converge timing/DRC/Congestion Mitigation/Low Power optimization of the blocks.
  • Mentor Junior Engineers.

Principal Application Engineer

Cadence Design Systems, Bangalore
07.2018 - 08.2021
  • PD tool support to a Tier 1 Semiconductor company. o Run benchmarks to achieve best PPA on a multi-million instance design. o Hands on experience in 11nm/7nm/5nm nodes.
  • Interact with customer to understand and resolve tool and Design related issues.
  • Integrate new tool features and methodology to customer flow.
  • Interface between R&D and customer to drive tool and methodology enhancements

Senior Application Engineer

Synopsys India Pvt Ltd, Bangalore
04.2016 - 07.2018
  • Synthesis, Physical Design and STA experience on different customer designs to achieve varying PPA.
  • Experience in different deep submicron technologies, 28nm/16nm/12nm/10nm/7nm.
  • Drove several customer benchmark engagements to success
  • Created and delivered product portfolios to customers
  • Created and delivered executive summary to key customers
  • Traveled onsite for presales support for critical customer engagements
  • Worked with different BU resources to achieve positive benchmark results for several customer

Component Design Engineer

Intel India Technology Pvt Ltd, Bangalore
05.2011 - 04.2016
  • In this role, have implemented and deployed P&R, Low power and timing sign off methodologies and flows for multiple technology nodes with varying design complexities and challenges.
  • Have defined, implemented and deployed Low power checks and QOR indicators to ensure zero silicon failures due to flow/methodology issues.
  • Have performed Tool QA of multiple versions of Synopsys Design compiler and IC compiler, which was instrumental in deploying the SYN/P&R flow/methodology with greater confidence.
  • Interaction with internal customers and designers to understand the requirement and provide solutions and checkers for flow/methodology issues.
  • Interaction with external vendors, Synopsys and Atrenta, to resolve tool and methodology related bugs and issues.
  • Implementation and deployment of Low power isolation and level shifter checks to catch design/implementation related issues.
  • Maintain and perform obfuscation/audit of the database to be shipped to vendor for bug fixes and enhancements

Intern

Intel India Technology Pvt Ltd, Bangalore
05.2010 - 04.2011
  • In this role, have implemented and deployed P&R, Low power and timing sign off methodologies and flows for multiple technology nodes with varying design complexities and challenges.
  • Have defined, implemented and deployed Low power checks and QOR indicators to ensure zero silicon failures due to flow/methodology issues.
  • Have performed Tool QA of multiple versions of Synopsys Design compiler and IC compiler, which was instrumental in deploying the SYN/P&R flow/methodology with greater confidence

Service Engineer

Wipro GE Healthcare Pvt Ltd. Hyderabad
08.2005 - 12.2008
  • In my role in Wipro GE, I took care of Installation and maintenance of higher end CT scanners, addressing technical issues of customers and supporting and managing vendor engineers for lower end CT scanners.
  • Support peers in service and troubleshooting issues with Cathlabs and MRI scanners.
  • Provide feedback to R&D on issues, bugs and enhancements

Education

BE (Medical Electronics) -

Sri Krishna Institute of Technology, Vishveswaraiah Technological University, Bangalore

Master of Science (VLSI CAD) -

Manipal Centre for Information Science, Manipal Academy of Higher Education (MAHE), Manipal

Skills

Low power flows/Methodologyundefined

Tools Used

  • EDA, Cadence Innovus/Genus/Voltus, Synopsys DC/ICC/ICC2/PT
  • Others, C, TCL, Perl, Verilog, UNIX

Timeline

Senior Staff Engineer

Marvell India Pvt Ltd
09.2021 - Current

Principal Application Engineer

Cadence Design Systems, Bangalore
07.2018 - 08.2021

Senior Application Engineer

Synopsys India Pvt Ltd, Bangalore
04.2016 - 07.2018

Component Design Engineer

Intel India Technology Pvt Ltd, Bangalore
05.2011 - 04.2016

Intern

Intel India Technology Pvt Ltd, Bangalore
05.2010 - 04.2011

Service Engineer

Wipro GE Healthcare Pvt Ltd. Hyderabad
08.2005 - 12.2008

BE (Medical Electronics) -

Sri Krishna Institute of Technology, Vishveswaraiah Technological University, Bangalore

Master of Science (VLSI CAD) -

Manipal Centre for Information Science, Manipal Academy of Higher Education (MAHE), Manipal

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P.N.THIRUMALESH Senior Staff Engineer