Srikant G Kadadevar
Bangalore
Summary
Technical lead for QA of design flows and methodologies, driving roadmap for Flow Qualification Team. Enhanced automation and stabilized test management, focusing on analog flow qualification improvements. Significant contributions in Analog EDA development, enhancing architecture and simulation capabilities in Direct Power Injection tool. Extensive experience at Texas Instruments and National Semiconductor, specializing in SKILL-based automation, ESD simulation tool development, and GUI testing in Virtuoso.
Overview
19
19
years of professional experience
Work History
Senior Staff Analog EDA and QA Engineer
Infineon Technologies Private Ltd
Bangalore
05.2016 - Current
- Architecture Improvement and Driving Roadmap for Flow Integration Tests.
- Qualification of analog flows and IP integration.
- IP transfer of analog domain IP to digital and vice versa.
- Basic know-how of GENUS and INNOVUS flows (RTL to GDS)
- Drive FinFET qualification for both flows and design packages.
- Scalable test infrastructure to handle complicated, robust use cases.
- Enable data management, a standardized QA structure, and automation in the Quality Assurance framework.
- Proposal and driving of implementation for new methodologies and tools for QA.
- Build a team of six people from scratch, mentoring, guiding, and leading as a tech expert, covering analog and digital tools and methodologies.
- Currently, a proposal is under discussion to automate template-based schematic and layout generation for analog device qualification.
- Strong Analog EDA Fundamentals:
- Enabled parallel simulation based on Ocean scripting within the environment of the Direct Power Injection setup, and improved simulation run time.
- Improve the overall architecture, and enable automatic coverage generation and code quality improvement.
- Propose and develop a Cadence SKILL-based methodology to automatically generate schematics for the list of analog devices, with a generic test case.
Analog Sr EDA Engineer
Texas Instruments Corporation and National Semiconductor
Bangalore
10.2007 - 04.2016
- Development of tools and methodology for ESD dynamic simulation, schematic test bench automation, ADE automation, and regression simulation infrastructure.
- Contribution to the development of digital flow for analog top designs.
- My responsibility was synthesis flow development and support.
- Productivity enhancement projects, which include Cadence SKILL-based automation scripts for design teams.
- IBIS model generation for simple and complex differential buffers.
- Involved in flow and methodology development for the IBIS model generation tool to support complex differential buffers.
- Testing and evaluation of the internal spice simulator for the support of VerilogA models.
Design Engineer (Mixed Signal Design)
Qualcore Logic
Hyderabad
03.2006 - 09.2007
- Design Tx and Rx for USB 1.1 with OTG block in UMC 065UM for SP and LL process.
- Design of a level shifter, crystal oscillator, and on-chip low-power oscillator design.
- IBIS model generation for simple and complex IO cells.
- Standard cell characterization (timing and power).
Education
PG DIPLOMA - VLSI Design
01.2006
Duration: 18 weeks
B.E - E & CE
01.2005
GPA: 72.2 %
XII - (CBSE)
01.2001
GPA: 67.00%
X - (CBSE)
GPA: 65.80%
Skills
Technical skills
- Expert in analog EDA development and automation based on the Virtuoso platform
- Basic analog test case development and layout generation based on Layout XL
- Cadence SKILL/Ocean-based automation
- Practical knowledge of GENUS and INNOVUS flows (RTL to GDS)
- Analog verification based on ADE, Spectre, and Spice simulation
- Know-how of IP transfer tooling to deliver analog IP to digital on top design and vice versa
- IBIS model generation
- Tools and methodologies
- Virtuoso Schematic and Layout XL editor
- Virtuoso ADE, Explorer, Spectre, and Spice Simulation setup
- Calibre DRC and LVS
- Quntus QRC/Av extracted view generation pre- and post-layout simulations
- Basic understanding of genus, Innovus (RTL 2 GDS)
- Expert on Cadence SKILL/OCEAN scripting
- Basic programming with Shell script, Perl, and Python
- Totem EM/IR Drop Analysis, ESD Simulation
- Data management tools like GIT and BitBucket
Non-Technical skills:
- Overall, I am the managerial lead for the QA team, helping with debugging, collaboration, and general guidance
- Cross-functional collaboration
- Process improvement within the QA domain
- Willing to learn new methodologies and flows
- EX: Drive and enable data management, Bitbucket, and Jira integration within QA infrastructure
Leadership skills
- Mentor and build a QA team of six people across analog and digital domains from scratch
- Sub PJM role, which involves resource management, sprint planning, risk assessment, and task scheduling
- Drive RCA using the 5 Whys or an equivalent methodology, and drive action items
- Stand by the team both technically and emotionally to motivate and guide the team
Languages
Kannada
First Language
English
Advanced (C1)
C1
Work Type
Full TimePart TimeContract WorkWork Location
On-SiteRemoteHybridTimeline
Senior Staff Analog EDA and QA Engineer - Infineon Technologies Private Ltd
05.2016 - Current
Analog Sr EDA Engineer - Texas Instruments Corporation and National Semiconductor
10.2007 - 04.2016
Design Engineer (Mixed Signal Design) - Qualcore Logic
03.2006 - 09.2007
Sandeepani School of VLSI Design - PG DIPLOMA, VLSI Design
B.E.C. - B.E, E & CE
Sainik School Bijapur - XII, (CBSE)
Sainik School Bijapur - X, (CBSE)
Awards and Recognitions
- Won best poster in ITECH Days for 'Regression Environment challenges for Analog Mixed Signal Designs'
- Received Best auditee award for the internal audit of our team
- My work was featured for poster in the internal technical conference of TI – TIITC-2013
- Three of my works were featured for posters in the internal technical conference of TI – TIITC-2013 and TI – TIITC-2014
- Awarded for contributing to the development of internal simulation tool to support for VerilogA models
- Recognized for contributing efficiently to productivity enhancement projects
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