As an innovative thinker and problem solver, i am detail-oriented and analytical with a creative and strategic approach to planning.i am tech-savvy , enthusiastic ,passionate about continous improvement and driven by curiosity and improvement.
Block level Implementation - ORCATOP 32-bit Multi voltage processor (ICC-2) 28nm, 01/01/24, Physical implementation of a block-level design (Netlist to GDSII) at 28nm technology, using 40 macros and standard cells 52k., Clock frequency of 435MHz., Supply voltage of 0.75V and 0.95V using 9 metal layers + MRDL., IR-drop 5., Operating voltage area and area 70mm2., Synopsis IC compiler (IIC2) PLL divider, 16nm present., 16nm technology, 12 layers, 153 macros, 2.2M cell count, 425MHz frequency., Synthesis, floor planning, timing analysis (time runs + fixes)., DRV (max trans, cap, fanout), IRRV fixes, scripting., Fusion compiler, Primetime, Calibre, StarRC.
Lucas-TVS Ltd,Puducherry ( 2017-2018)
Quality auditor.