Summary
Overview
Work History
Education
Skills
Areas Of Interest
Positions Of Responsibility
Scholastic Achievements
M.Tech Projects And Seminars
Extracurricular Activities And Hobbies
Training
Timeline
AdministrativeAssistant
Shivajee Tiwari

Shivajee Tiwari

DFT Engineer
Piro

Summary

Developed critical thinking and problem-solving abilities in fast-paced engineering environment. Brings strong foundation in analytical and technical skills, adaptable across various fields. Seeking to transition into new role where these transferrable skills can contribute to innovative solutions and project success.

Overview

8
8
years of professional experience

Work History

DFT Engineer

Intel
07.2024 - Current

Worked on two different projects (Core and Uncore).

I gave a presentation on different topics, mainly related to the basics of memory and the basics of MBIST.

I got the opportunity to work on MBIST insertion and validation.

I also got an opportunity to work on JTAG.

Deputy Executive Engineer

NLC India Ltd.
01.2018 - 11.2019
  • Company Overview: Govt. of India Enterprise
  • Completed full training working as GET for one year then got successfully regularized as Dy. Executive Engineer for Thermal Power Plant
  • Worked as Deputy Executive Engineer in Thermal Power station-2

Education

M.Tech. - Integrated Circuit and Systems

Indian Institute of Technology Bombay
Mumbai, India
04.2001 -

Graduation - Electronics & communication Engineering

NIT Jalandhar
06-2015

Skills

DFT

Areas Of Interest

  • Digital VLSI Design
  • DFx (Design for Testing, debugging etc.)
  • MBIST
  • JTAG
  • TAP
  • SSN
  • SCAN
  • ATPG
  • Computer Architecture
  • Testing and Verification
  • Data and Hardware Security

Positions Of Responsibility

Research Assistant in MBF Project in EE Department, Prof. Saravanan V., IITB, 2021-08-01, present, Maker Bhavan Foundation has contributed for ELL(Laboratory) and CC(Collaborative classroom), ELL consists of equipment like 3-D printer, Laser cutter etc., in which I helped/trained some UG/PG students for packaging/other projects & managed CC as well.

Scholastic Achievements

  • Secured 99.86 percentile in GATE-2017 ECE among 142 thousand appeared candidates, 2017
  • Secured 99.29 percentile in GATE-2019 ECE among 105 thousand appeared candidates, 2019
  • Secured AA grade in 3 courses, most relevant one being Hardware Description(EE721) at IIT Bombay

M.Tech Projects And Seminars

  • M.Tech Project: Implementation of PUF based data Security algorithm using symmetric keys for Neuro-stimulation Devices, Prof. Laxmeesha Somappa, Electrical Engineering, IIT Bombay, 2023-06-01, present, To design Power and Area optimized attack resilient PUF architecture for CRYPTO algorithms to Secure Neuro-stimulation chip, Reviewed papers and implemented some PUF architectures on XILINX PYNQ-Z2 FPGA board using XILINX-Vivado for comparative analysis, Demonstration of different architecture of (PUF) and doing comparative analysis after implementing on FPGA using XILINX-Vivado and Altera-Quartus, Designing Suitable PUF architecture for Generation of Crypto. KEY using Verilog, based on Attack resilient, Implementation of AES Algorithm using above KEY for securing DATA in Neuro-stimulation device on FPGA, Optimization of Area and Power for above some proposed architectures then implementing same with Asymmetric Crypto. Algo., Finding best architecture for security of NEURO-STIMULATION device in terms of optimum Area, Power and Attack Resilient etc.
  • M.Tech Seminar: Review of data security in biomedical devices, Prof. Laxmeesha Somappa, Electrical Engineering, IIT Bombay, 2023-01-01, 2023-04-30, Reviewed literature and recent Techniques for DATA Security and Hardware Security framework using PUF based architecture and CRYPTOGRAPHY, Reviewed different types of PUF architectures like Arbiter, RO PUF etc. and their comparative analysis, Studied Generation of Cryptography KEY by using different PUF architecture, Explored options for using above KEY in different Symmetric and Asymmetric Cryptography algorithm

Extracurricular Activities And Hobbies

Mentor in College Representative Internship Program, Under Abhyuday, IITB, Mentored 3-4 College groups participating for different Social activities under CR program 2022-23, Counselled Underprivileged students in an offline mode under Abhyuday, IIT BOMBAY'S Career counselling program 2021-22, Co-Head, Event Management at techNITI'13, NIT Jalandhar, Worked as Organizer of the tech-fest of NIT J i.e. techNITI in which I managed some of the events of this edition of fest., Trekking, Cycling, Badminton, Listening to music, Watching movies, Running, Gyming

Training

  • Hardware Description Languages at IIT Bombay
  • Complete GPU Training (Compute related) at Intel
  • DFT at Intel
  • VLSI Design at IIT Bombay
  • Testing and Verification of VLSI Circuits at IIT Bombay
  • Processor Design at IIT Bombay
  • Algorithmic Design of Digital Systems at IIT Bombay

Timeline

DFT Engineer

Intel
07.2024 - Current

Deputy Executive Engineer

NLC India Ltd.
01.2018 - 11.2019

M.Tech. - Integrated Circuit and Systems

Indian Institute of Technology Bombay
04.2001 -

Graduation - Electronics & communication Engineering

NIT Jalandhar
Shivajee TiwariDFT Engineer