SK ABDUL FAHEMID
Bangalore
Summary
I have 7.5+ yrs Experience as Senior Verification Engineer with a demonstrated history of working in the semiconductors industry. Have a strong verification skill like constraints-based Environment testing and debugging, for successful ASIC and FPGA Development. Developed a Test-bench architecture for sequences, deriver, monitor and scoreboard using System Verilog language Framework using (UVM-Universal Verification Methodology). C and C++ and the design end using language Verilog/HDL.
I have extensive experience with various protocols such as AXI-3, AXI-4, I2C, I3C, SMBUS, AMBA-CHI5, PCIe, ETHERNET, and SPI. This diverse protocol exposure highlights his versatility in handling a wide range of projects and scenarios within the VLSI domain.
Overview
9
9
years of professional experience
Work History
Senior Verification
WIPRO PVT.LTD-MC Lena for NXP client
Bangalore
11.2022 - Current
- created a Test cases Ethernet based vector Extension.
- Debugging and Verifying the design against SPIC Simulator.
- Implantation of GLS from scratch.
Verification Engineer
L&T Technology Services - WHS_HALK-S3M Interface for Intel Client
Banglore
09.2021 - 10.2022
- Created testplan for S3M
- Understanding s3m bring up in WHS arc-based C test Development.
- Implementation for SMBUS, SPI FLASH, test case.
- Debugging and Verifying the design against I2C and PCIe.
- Implement a GLS from Scratch.
- Intel – x-propagation excluding incomplete test point and debug test case.
Verification Engineer
L&T Technology Services - Ethernet-800G for Cyient Client
Banglore
12.2020 - 10.2021
- Created VIP UVM Component like Driver, Monitor, Scoreboard and Predictor
- Implementation test case for scoreboard.
- Automatic FEC/CRC generation and monitoring/checking.
- crated a constraint based random test cases.
- 100G lane round robin is followed on byte basis.
Verification Engineer
Alpha-Numero pvt.ltd -Ebonics / DO-254-777x for Boeing client
Ahmadabad
03.2019 - 02.2020
- Development a scoreboard and Arbiter.
- Implantation Test Case multiple pcm_reset.
- Test Plan creation and finding a link Error updating.
- Review Lead of getting all the Test Procedure reviewed by Reviewer following the process mentioned under DO-254 standards Create prediction logic.
- Created Functional Coverage and Assertion Plan for Vector Processing Unit.
Verification Engineer
Alpha-Numero pvt.ltd-Analog Discovery With Hip Board for Cadence client
Ahmadabad
11.2018 - 02.2019
- Developing test bench. Understanding the architecture and developing test scenarios according to the verification plan.
- To build the tb for driver, sequencer and monitor, sequences.
- Functional coverage analyzes through the coverage report make a 100 %.
- Monitor debugs using developed test cases and report AHI report with wave from automated Generate.
Verification Engineer
CSS CORP PVT. LTD -SG300-52p-28p for CISCO client
Bangalore
08.2017 - 07.2018
- Understanding the architecture and developing test scenarios according to the verification plan
- To Build the test bench and writing the sequences.
- Implement a coverage and predictor as per a requirement.
- Designed and analyzed test bench environment and perform required modifications.
Verification Engineer
CSS CORP PVT. LTD - wireless and Monitor for Honeywell Client
Banglore
01.2017 - 07.2017
- Write a Verification Environment generate a signal and stimulate through DUT.
- DUT under the test Verification IP to a Signals and environment through the coverage.
- The overall design, preparing a verification plan, creates test-benches, debug verification results.
Design Engineering
CSS CORP Pvt. Ltd- DDR3 for Feature Electronic Client
Banglore
06.2015 - 12.2016
- create test cases to verify the BUS and Interrupts.
- The design unit dynamically switches between read and writes operations.
- Synthesis tools can detect RAM designs in the HDL code.
Design Engineer
CSS CORP Pvt. Ltd - USB_3.0 for True Chip client
Banglore
01.2016 - 06.2016
- Synthesis tools can detect RAM designs in the HDL code.
- The design unit dynamically switches between read and writes operations.
- Assigned to create test cases to verify the BUS and Interrupts.
- As per the client Requirement or Specification implement a design.
Education
B-Tech (EEE) - Electrical Engineering
Guru Nanak Institute Of Technology (WBUT)
Kolkata, North 24 pargana sodhpur08-2014
Diploma (EE) - Electrical Engineering
Balasore School of Engineer (SCTE & VT)
Balasore, Odisha 07-2010
ITI (Electricians) - Electrical Engineering
Balasore Technical School (NCVT)
Balasore ,Odisha07-2006
10th (All Subject) - Middle School Education
Balasore Zilla School
Balasore, Odisha01.2004
Skills
- Implemented the TB Environment , constraints-based Environment, Testing and debugging, for successful ASIC and FPGA Development using a Language Verilog/HDL,System Verilog/VHDL language Framework using (UVM-Universal Verification Methodology),C, C, Python, TCL
- Protocol:-I2C,I3C, AXi-3/4, SPI, Ethernet, UART, PCIe
Languages
Urdu
First Language
English
Proficient (C2)
C2
Hindi
Proficient (C2)
C2
Timeline
Senior Verification
WIPRO PVT.LTD-MC Lena for NXP client
11.2022 - Current
Verification Engineer
L&T Technology Services - WHS_HALK-S3M Interface for Intel Client
09.2021 - 10.2022
Verification Engineer
L&T Technology Services - Ethernet-800G for Cyient Client
12.2020 - 10.2021
Verification Engineer
Alpha-Numero pvt.ltd -Ebonics / DO-254-777x for Boeing client
03.2019 - 02.2020
Verification Engineer
Alpha-Numero pvt.ltd-Analog Discovery With Hip Board for Cadence client
11.2018 - 02.2019
Verification Engineer
CSS CORP PVT. LTD -SG300-52p-28p for CISCO client
08.2017 - 07.2018
Verification Engineer
CSS CORP PVT. LTD - wireless and Monitor for Honeywell Client
01.2017 - 07.2017
Design Engineer
CSS CORP Pvt. Ltd - USB_3.0 for True Chip client
01.2016 - 06.2016
Design Engineering
CSS CORP Pvt. Ltd- DDR3 for Feature Electronic Client
06.2015 - 12.2016
B-Tech (EEE) - Electrical Engineering
Guru Nanak Institute Of Technology (WBUT)
Diploma (EE) - Electrical Engineering
Balasore School of Engineer (SCTE & VT)
ITI (Electricians) - Electrical Engineering
Balasore Technical School (NCVT)
10th (All Subject) - Middle School Education
Balasore Zilla School
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