Summary
Overview
Work History
Education
Skills
Leadership & Impact
Timeline
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Snehal Kate

Bengaluru,Karnataka

Summary

Experienced SoC Power and Performance Engineer with 8+ years in power modeling, low-power SoC architecture, and system-level optimizations. Demonstrated success in leading cross-functional teams, driving power convergence, and delivering innovative solutions for edge servers, AI accelerators, and networking platforms. Adept at thermal analysis, PDN optimization, and cutting-edge low-power methodologies for world-class semiconductor products.

Overview

11
11
years of professional experience

Work History

SoC Power and Performance Engineer

Intel
01.2020 - Current
  • Engineered accurate power/performance models for advanced edge server SoCs, enabling superior pre-silicon projections and benchmarking.
  • Led power convergence and modelling on planar as well as Foveros architectures.
  • Generated detailed power maps and thermal analysis to drive optimal cooling and reliability.
  • Optimized PDN through ICCmax analysis across multiple IP and subsystems.
  • Designed and implemented power modelling for NIC and AI accelerator chip let, advancing overall system optimization efforts.
  • Championed cross-functional collaboration from process to platform for robust power delivery.
  • Developed and validated UPF for Compute, Memory, IO, and Coherent fabrics, ensuring full-chip low-power compliance.
  • Led implementation of innovative power intent methodologies and collaborated with architecture, physical design, and sign-off teams to reach aggressive power targets.

Digital Design Engineer

Texas Instruments
07.2015 - 03.2017
  • Characterized standard cells and compilers for accurate power, delay, and leakage, using industry-leading tools like Cadence Spectre and Liberate.
  • Conducted exhaustive constraint and power calculations for library development.

Project Assistant (VLSI)

Indian Institute of Science (IISc)
11.2014 - 12.2015
  • Developed high-efficiency Verilog RTL for arithmetic hardware accelerators.

Intern, Power Estimation

Intel
01.2015 - 06.2015
  • Designed and deployed front-end power estimation flows, achieving measurable reduction in power consumption.

Education

M.Tech. - VLSI Design

Vellore Institute of Technology (VIT)
Vellore, Tamilnadu
06.2015

Skills

  • SoC Power Modelling & Optimization
  • UPF Development & Validation
  • System-Level Power Architecture
  • Power Delivery Network (PDN) Analysis
  • Performance Benchmarking & Projections
  • Cross-functional Team Leadership
  • EDA Tools: Synopsys VCS, Design Compiler, Cadence Spectre, Liberate
  • Scripting: Python, Perl, Shell, TCL
  • Verilog & VHDL
  • Power modelling/debugging, SoC power correlation
  • Power delivery optimization
  • EDA: PowerBI, Synopsys static checks, VCS, Design Compiler, Cadence Spectre/Liberate
  • Languages: Verilog, VHDL, Python, Perl, Shell, TCL

Leadership & Impact

  • Proactive leader of multi-disciplinary teams to deliver architectural and system power excellence.
  • Received Impact awards for overcoming Power/Thermal challenges
  • Recognized for spearheading key power modelling initiatives for next-generation SoCs

Timeline

SoC Power and Performance Engineer

Intel
01.2020 - Current

Digital Design Engineer

Texas Instruments
07.2015 - 03.2017

Intern, Power Estimation

Intel
01.2015 - 06.2015

Project Assistant (VLSI)

Indian Institute of Science (IISc)
11.2014 - 12.2015

M.Tech. - VLSI Design

Vellore Institute of Technology (VIT)

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