Pavan Ambati
Bengaluru
Summary
Seasoned Lead Engineer with a resourceful, hardworking, and quality-driven mindset. Proactive in tackling equipment and system issues to maintain operational status. Top-notch leader and project manager with an organized and methodical approach. with expertise in SOC-level power estimation and analysis, specializing in Unified Power Format (UPF) and conducting thorough structural checks. Proven track record of improving project efficiency through the implementation of innovative power estimation tools, resulting in significant advancements.
Overview
7
7
years of professional experience
Work History
SOC Power Lead Engineer
Qualcomm India Pvt. Ltd
03.2018 - Current
- UPF based power cells insertion and validation, using conformal low power (CLP) tools at RTL level, Structural checks on all SYNTH stages and give final sign off on final opt stage for Physical Implementation.
- SOC level UPF generation and validation with VCS tool , PARTL UPF validation with VCLP (Synopsys) , checks DB missing issues and UPF issues and CSN missing issues.
- POWER SENSOR: Sensors connectivity implementation and Placement based on floorplan and SPEC creation.
- LEAKAGE POWER: estimate leakage power at SOC flat level. Give feedback to PD on VT usage and Analyze power hungry blocks.
- Power Budgeting: based on Product definition, will define leakage power budget for SOC flat and sleep current.
- Power Optimization techniques implementations (like rail collapse, Power Gating, Clock Gating, Multi- Vth, Multi - VDD..Etc.)..
- Dynamic Power : Based on use case and data toggle rate, Identify the total dynamic Power and observe power optimization logic in the design and share feedback to DV (vector).
- Clock Tree Power Estimation: estimate dynamic power consumption at the SOC level, performed using PTPX. Identify highest clock tree power clocks and share feedback to STA team.
- Peak Power: Budgeting/Analyzing/Estimation for peak power number for each rail to identify PMIC buck allocation and identify mitigation schemes.
- Managed full project with minimal resource and quality release of UPF for dependent stake holders.
Education
Master of Technology (MTech) - VLSI Design
Vignan's University
Guntur, AP07.2017
Bachelor of Technology (B.Tech.) - Electronics and Communication
Vignan's University
Guntur, AP 08.2015
Skills
- Power Estimation
- Power Budgeting
- Power optimization techniques
- Power analysis
- UPF IEEE 1801
- PERL scripting
- Conformal Low Power
- VCLP
- VCS elaborations
- VERDI
- PTPX
- Power Artist
Languages
English
Telugu
Hindi
Interests
Playing Cricket, Watching Movies
Expertise summary
Areas of Experience: Power optimization techniques, Power analysis, low power design, structural power checks, power estimation, UPF and Unified Power Format (UPF), Conformal Low Power (CLP), PTPX
Publications
- A NEW APPROACH FOR RFID TAG DATA READING IN FPGA BY USING UART AND FIFO, International Journal of Engineering and Manufacturing (IJEM), 10.5815/ijem, 8, 2, 03/2018
- FPGA IMPLEMENTATION OF MAC UNIT USING VEDIC MULTIPLIER AND PARALLEL PREFIX ADDERS IN SPARTAN 3E, International Journal Control Theory and Application, 0974-5572, 21, 2017
Timeline
SOC Power Lead Engineer
Qualcomm India Pvt. Ltd
03.2018 - Current
Master of Technology (MTech) - VLSI Design
Vignan's University
Bachelor of Technology (B.Tech.) - Electronics and Communication
Vignan's University
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