Devansh Paradkar

RTL Design Engineer

Bengaluru,KA

Summary

I work in VLSI Front end design which deals with RTL, Low power architecture, power intent design and implementation, Clk controller design, power estimations and optimization at system and use-case level. I further am looking forward to expanding my skills in knowledge in low power design, clock and reset architecture, AMBA bus protocols.

Overview

years of professional experience

years of post-secondary education

Languages

Work History

SOC Design Engineer

Qualcomm India Pvt. Ltd

Hyderabad

06.2021 - Current

Spearheaded power intent definition using UPF and power signoff processes for complex SoC designs, ensuring adherence to industry standards and guidelines
Conducted deep dive power violation checks using Conformal Low Power (Conformal Low Power - CLP ) to ensure power integrity and compliance
Played a key role in SOC integration and connectivity.
Led low power verification efforts, employing VCS and Verdi tools to verify power-aware RTL.

Education

Master of Engineering - Microelectronics

Birla Institute of Technology And Science

08.2019 - 06.2021

Bachelor of Technology - Electronics and Communication Engineering

Nirma University

Ahmedabad, Gujarat

Skills

UPF (Unified Power Format)undefined

Accomplishments

Static Timing Analysis - Udemy - Principles of Communication System - IIT Kanpur
Projects - Worked on power-aware components into a complex SoC design targeting Mobile, Automobile, wearable chips, at different stages of Design cycle, RTL, Netlist which involves deep-dive into UPF/CLP low power signoff
Languages - Proficiency in English, Hindi, Marathi.

Playing Tabls, Cricket, Chess etc

Interests in sports and high intensity workouts.

Timeline