Fitness, GYM
SOHEL HAQUE
VLSI Design Engineer
Bangalore
Work Preference
Summary
Result-oriented VLSI Circuit Design Engineer with 7 years of experience in SRAM memory design projects. Expertise in leading in-house and cross-functional teams to deliver high-quality memory solutions on time and within budget. Recognized for a positive approach and unwavering dedication, with a strong enthusiasm for tackling new challenges in the semiconductor industry. Committed to leveraging extensive skills and experience to drive advancements in the evolving semiconductor landscape.
Overview
9
9
years of professional experience
Work History
SRAM MEMORY DESIGN, STAFF
Synopsys
11.2023 - Current
- Developed UHD1PRF Compiler in N5 Automotive Process with 6% area optimized at the chip level for the customer to use in UFS applications. Managed the project as a lead, with decision-making for the architectural design changes, to achieve the area target.
- Identified bottlenecks in existing verification flows, leading to significant improvements in overall efficiency.
- Streamlined documentation processes by creating standardized templates for test plans and reports, saving valuable time during project phases.
- Developed HPCkit in the N3A node with a lot of customizations on the base design as per the PPA needs of the customer. Implemented FBL+Rebuffer architecture to achieve a 10% area gain, with a 20% dynamic power reduction.
- Contributed to successful tape-outs by rigorously verifying design functionality under various operating conditions.
- Contributed to the ongoing success of the organization by actively participating in recruitment efforts, interviewing candidates, and providing input on hiring decisions.
SRAM MEMORY CIRCUIT DESIGN, SR
Synopsys
05.2021 - 10.2023
- Lite Dual Rail Feature Audit across all memory compilers in N5 Customer Base. Post verification there was a deal tie-up for the specific usage by TI for this feature
- Interface Dual Rail Level Shifter Feature based Dual Rail Memory Compiler development in N3P Platform. N3P was mature compared to N3E and we developed the design in High Speed 2 Port RF Memory with a significant improvement in PPA compared to existing Embedded Dual Rail. Delivered TC also as part of the program whose initial results are a great success
- Skilled at working independently and collaboratively in a team environment.
- Organized and detail-oriented with a strong work ethic.
SRAM MEMORY CIRCUIT DESIGN, JR
Synopsys
07.2017 - 04.2021
- Design and Verification Lead - High Density Dual Port Design in N5. One of the challenging projects of my Carrer as design was restricted by the complexity of the bitcell. The bitcell behavior drastically changed from N7 process and with the complexities of coupling scenarios in DP bitcell made the impact in PPPA very distinguishable. Designing and tuning the memory was difficult but we achieved the closure and post silicon success results brought fruits to our hard work
- Worked on the atspeed verification of various memory compilers in initial part of my Carrer like UHD2PRF, UHD1PRF, HSSP. HDSP, HS1PRF, HD1PRF in N7, TS12, TS16 process as part of QA verification during Compiler Release. This made me know in and out design of the memory architectures as we developed stimulus and wrote measurements to verify these memories
- Self-motivated, with a strong sense of personal responsibility.
- Excellent communication skills, both verbal and written.
Education
BTECH - Electrical & Electronics Engineering
NIT TRICHY
Tiruchirapally 04.2001 -
Skills
Applying AI tools for predictive analysis of memory
Project management with resource optimization
In-depth analysis of customer solutions
Designing solutions for silicon debugging architecture
Proficient in XA,HSPICE,VERDI simulation tools to debug and analyze
Customer data visualization
Managing meeting schedules
Static Timing Analysis
Proficient in analog/mixed-signal memory systems
Solid foundation in digital and analog design techniques
Unix scripting using TCL and Perl
Interests
Timeline
SRAM MEMORY DESIGN, STAFF
Synopsys
11.2023 - Current
SRAM MEMORY CIRCUIT DESIGN, SR
Synopsys
05.2021 - 10.2023
SRAM MEMORY CIRCUIT DESIGN, JR
Synopsys
07.2017 - 04.2021
BTECH - Electrical & Electronics Engineering
NIT TRICHY
04.2001 -
Certifications
- VLSI Training Course, CTTC Bhubaneshwar
- SNPS GLOBAL EM Rewards: - Best Write Time Debug and Solution for DP Memory
- SNPS ITVP Technical Committee: - Recognized for presenting key topics related to DP bitcell complexity design and Statistical Monte Carlo Analysis
- Regular Quarterly PAT Award Winner in Bangalore team for exceptional efforts in debug and closure of regular projects
Scripting
· Shell Scripting
· TCL
· Perl
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Personal Information
Languages
English
Bilingual or Proficient (C2)
Hindi
Bilingual or Proficient (C2)
Bengali
Advanced (C1)