Vanshika Kumawat
Kotputli
Summary
Memory Design Engineer specializing in bit cell analysis, compiler flow enablement, and functional verification. Proven ability to collaborate across teams to enhance memory compiler reliability and performance. Demonstrated success in optimizing design processes and ensuring high-quality outcomes in memory development projects.
Overview
2
2
years of professional experience
Work History
Sr. R&D Engineer, SRAM Design
synopsys india pvt. ltd
Noida
01.2023 - Current
- Conducted bit cell analysis to evaluate trends and behaviors under varying conditions.
- Facilitated memory compiler flow enablement, ensuring design readiness for projects.
- Executed functional verification of memory compilers, resolving issues efficiently.
- Coordinated integration efforts with cross-functional teams to align features smoothly.
- Collaborated with team members to achieve project objectives and adhere to deadlines.
Education
Master of Technology - VLSI&ES
Delhi Technological University
New Delhi06-2023
Skills
- Bit cell analysis
- Memory compiler flow
- Functional verification
- SRAM design
- Digital VLSI design
- UNIX operating system
- CMOS technology
- Digital circuit design
Affiliations
- Helped organize team events and activities.
- Mentored new joiners,
Hobbies
- Listening music and exploring new places
Timeline
Sr. R&D Engineer, SRAM Design
synopsys india pvt. ltd
01.2023 - Current
Master of Technology - VLSI&ES
Delhi Technological University