Summary
Work History
Education
Skills
Accomplishments
Tools Knowledge
Papers Published
Personal Information
Languages
Hobbies and Interests
Projects
Timeline
Generic
SOUMI KARMAKAR

SOUMI KARMAKAR

Kolkata

Summary

Dreamer to be an Expert in VLSI Design

Work History

Verification Engineer

HCLTech(working for Cadence job)
  • Tested functionality, performance and compliance of each product against design specifications to maintain strong development standards and high customer satisfaction.

Education

B. Tech - Electronics & Communication Engineering

Institute of Engineering & Management
01.2021

Skills

  • Analog Circuits
  • Arduino
  • Knowledge of IOT-based system
  • Digital Circuits
  • Cadence Virtuoso

Accomplishments

  • Selected as a Special Winner at the Sankalp Hackathon
  • Received the ‘WIE’ best student award at the IEMENTECH, IEEE conference.
  • Selected 3rd position in model competition at the IEEE International Conference in the year 2019.
  • Selected at the final round of AICTE conducted ‘VISWAKARMA NATIONAL PROJECT COMPETITION’
  • Selected at the second round of L&T conducted Techgium all India competition and ANALOG DEVICES Conducted 2020

Tools Knowledge

  • Arduino
  • Cadence Virtuoso

Papers Published

  • Tropospheric Scintillation at Ku/Ka Band In Orographic Region, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTech48150.2019.8981105
  • Smart Bag for Women Safety, 2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTech51367.2020.9270046
  • IOT Based Air Discomfort Reliever, 2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), 10.1109/IEMTRONICS51293.2020.9216398
  • Self Sustained Village, 2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTech51367.2020.9270091
  • Grid Synchronized Solar Micro-Inverter, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTech48150.2019.8981216
  • Study of the effect of Air Pollution on Solar Power Generation Using Sun Simulator, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTech48150.2019.8981361
  • Brainwave Sensed Chromo Therapy Based Meditation Hub, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 110.1109/IEMENTECH48150.2019.8981010
  • Brainwave Sensing Device Based Musical Stress, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), 10.1109/IEMENTECH48150.2019.8981289

Personal Information

  • Date of Birth: 11/14/1996
  • Gender: Female
  • Religion: Hinduism

Languages

  • English
  • Hindi
  • Bengali

Hobbies and Interests

  • Art and craft
  • Listening to music

Projects

Working on:

Sw0101_ss8lpu project

Mainly focused on some design changes of  TX according to customer requirements and also validating the performance of that block and performing quality analysis. 

Worked on:

Cadence Intel 18A project:

 Design and performance analysis on ATB(Analog Test Bus) block and logic part of RESET IO block. In this project, I have used only core devices. So the blocks are overstressed design. 

ATB: ATB is used to probe internal voltages /currents from the IP. 

RESET IO: It is a single-ended driver(TX) and receiver (RX)reset cell. It also contains a POC (Power on Circuitry) cell which is used to generate a signal when VDD(power supply) is not present. 

ddr900_t5g project

 Worked and analyzed on Power switch Block. Power switch: It is used to reduce leakage by cutting the flow of current from the supply to the ground when the circuit is idle. 

ddr500_t3g  &ddr500_t5gp &ddr510_t5g projects: 

 Mainly focused on performance simulation, functional simulation, and reliability analysis of Reset cell and Analog Test Bus. For this project, functionality of ATB and Reset Io cell are the same as the Intel 18A project. But architecture is different.

 Microchip Joshua Tree 28nm project:

Worked and analyzed, made test benches of the following blocks 

a. Level Shifter Circuit 

b. 4 to 16 Decoder 

c. Transmission Gate 

d. Worked on PERC Run on Comparator top cell. 

The following CAD Tools have been used: Virtuoso Schematic Editor, ADE-XL, ADEL   

Timeline

Verification Engineer

HCLTech(working for Cadence job)

B. Tech - Electronics & Communication Engineering

Institute of Engineering & Management
SOUMI KARMAKAR