Verification Engineer
- Tested functionality, performance and compliance of each product against design specifications to maintain strong development standards and high customer satisfaction.
Dreamer to be an Expert in VLSI Design
Working on:
Sw0101_ss8lpu project:
Mainly focused on some design changes of TX according to customer requirements and also validating the performance of that block and performing quality analysis.
Worked on:
Cadence Intel 18A project:
Design and performance analysis on ATB(Analog Test Bus) block and logic part of RESET IO block. In this project, I have used only core devices. So the blocks are overstressed design.
ATB: ATB is used to probe internal voltages /currents from the IP.
RESET IO: It is a single-ended driver(TX) and receiver (RX)reset cell. It also contains a POC (Power on Circuitry) cell which is used to generate a signal when VDD(power supply) is not present.
ddr900_t5g project:
Worked and analyzed on Power switch Block. Power switch: It is used to reduce leakage by cutting the flow of current from the supply to the ground when the circuit is idle.
ddr500_t3g &ddr500_t5gp &ddr510_t5g projects:
Mainly focused on performance simulation, functional simulation, and reliability analysis of Reset cell and Analog Test Bus. For this project, functionality of ATB and Reset Io cell are the same as the Intel 18A project. But architecture is different.
Microchip Joshua Tree 28nm project:
Worked and analyzed, made test benches of the following blocks
a. Level Shifter Circuit
b. 4 to 16 Decoder
c. Transmission Gate
d. Worked on PERC Run on Comparator top cell.
The following CAD Tools have been used: Virtuoso Schematic Editor, ADE-XL, ADEL