Sunil Gudur

Working as lead CPU Sub-System as Lead, Delivered to Multiple SoC's.

• Understanding feature requests & providing timelines of deliverables.
• working closely with Core/SoC DV, DFT, BE, Emulation & SW, including bringup activities
• Lead team of 2 along with closely working with them for deliveries with quality.
• Deliverables including SWI/LPM & soc interactions.
• Good understanding of ARM Architecture.
• Good understanding of infra interactions & protocol knowledge needed for subsystem.

• Client Coherent Fabric design changes handled
• Leveling up understanding of coherency protocols used in design
• Understanding Data path from processor/cache/System Agent
• Understanding AddressMap
• Understanding Credit Loops from System Agent to Cache Agent and Vice-Versa for the C2U & U2C traffic
• Non-Coherent Path flow, for the transactions starting from Processor
• Coded Design Changes as required by uARCH for non-coherent event flows
• Coded Design Changes for credit flows
• Coded Changes for datapath flows
• Have good understanding of ring topology
• Handling spyglass lint cleanup and integration of subsystem with the interface changes because of design

• Worked on Integration on server class SoC.
• Post/pre silicon debug support
• Working closely with validation teams for pre silicon debugs for IO/UBOX components
• IO/UBOX/Cache components are placed on 2D mesh coherent fabric
• Worked closely with validation teams to generate stimulus or using existing to not have any holes in the PLA Generation, PLA is a Black box for SW interactions on register access.
• Supported in post silicon debug for performance based & functional based debugs

• SoC Integration for Client Products & support pre/post-silicon teams
• Worked as Liaison for SoC & Memory generation team, understanding design requirements and quoting the memory team for equivalent memories and provide feedback on any collateral issues and provide insights to designer on the memory rtl
• Worked on multiple client projects, integrating Root-Complex, sideband, primary fabric, supporting pre-silicon teams, physical design, lint, cdc, timing teams to closure
• Supported Post Silicon Validation teams in effort in providing details of design for debug & clearing path for traffic moving along fabrics

• Worked on as a RTL design & Lead
• Lead a 3 member team, to provided RTL deliverables for Standard Cell Testchips
• Writing scripts in perl to generate, design to test standard cells for timing & functionality
• Writing glue logic for PLL, Thermal Sensor & processor monitor to test on silicon for characterization
• Working closely with verification/physical design/DFT teams, for the RLT deliverables
• Enabling Silicon and procuring & processing data for analysis, comparing against Libraries
• Worked as a team member in designing AHB2AXI Bridge