Suprith M

• 3+ years of experience as Physical Design Engineer.
• Hands on experience in Floor Planning, Power Planning, Placement, CTS and Routing and fixing the issues.
• Experience and good knowledge of Cadence tool - INNOVUS for Physical Design, GENUS for synthesis and TEMPUS for Timing Analysis
• Good Knowledge in scripting languages like TCL
• Experience in debugging and solving issues like congestion, timing analysis and fixing setup and hold violations, fixed DRVs
• Experience on various technology nodes including 22nm 12nm 7nm and 5nm
• Customer support on Digital Implementation and Reference Flow related issues and Validating the complete PnR flow for Reference Flows for better PPA benchmarking

Project 1: Demois Core Design

Tech Node : TSMC 4nm

Tools : INNOVUS and TEMPUS .

Macro count : 1486 ports with 187 macros, operate at 2.6 GHz.

Roles & Responsibilities:

• Floorplan was the main challenge for better QOR.

• Congestion was resolved by applying Blockages and Cell padding Techniques.

• Applied path grouping to clear the timing issue in placement stage.

• Having hands on experience about ECO stage such as clearing timing issues like DRVs setup and hold fixes.

Project 2: Ananke core Deign

Tech Node : TSMC 4nm

Tools : INNOVUS and TEMPUS

Macro count : 1499 ports with 59 macros, operate at 2 GHz.

Roles & Responsibilities:

• Responsible for Floor planning, Place & Route of the design, perform STA and bring the block to timing closure.

• Performed multiple Floorplan experiments to improve the timing and congestion.

• Fixed congestion using cell padding, routing blockage and applied Partial, Hard and Soft Blockages.

• Path groups and weights, bounds, skewing, bypassing cells to fix timing issues.

Project 3: DMA_MAC

Tech Node : TSMC 45nm

Tools : INNOVUS and TEMPUS

Macros: 7

No. of Std Cell: 23600

Frequency : 125 MHz

Roles & Responsibilities:

• Responsible for Physical Implementation – starting from Netlist to GDSII, including Floor planning, Placement,Clock Tree Synthesis, Optimization, Timing Closure

• Performed timing and congestion result at each stage in PnR flow and performed signoff checks like DRC and DRV fixing

Project 4: PICO_RV

Tech Node : TSMC 45nm

Tools : INNOVUS and TEMPUS

Instance Count: 25k

Frequency: 125 MHz

Roles & Responsibilities:

• Responsible for Floor planning, Place & Route of the design, perform STA and bring the block to timing closure.

• Applied placement techniques like partial blockage to reduce congestion.

• Genus Synthesis Solution with Stylus Common UI v20.1 Exam, Issued by Cadence Design Systems
• Basic Static Timing Analysis, Issued by Cadence Design Systems
• The Complete Course of TCL programming, Issued by Udemy
• UPF Power Aware Design and Verification, Issued by Udemy

• Best Student Award of Year, 2011, Thomas Memorial English High School
• Secured 6th Rank in PG Entrance Test