Summary
Overview
Work History
Education
Skills
Extra Curricular Activities
Disclaimer
Personal Information
Additional Information
Timeline
Hi, I’m

Vanshaj Garg

Sr. Firmware Engineer
Noida,UP
Vanshaj Garg

Summary

Results-driven Senior Firmware Engineer with over 7 years of experience architecting, developing, and optimizing embedded and system-level software across diverse platforms. Proven expertise in Embedded C/C++ with deep proficiency in debugging and development using Eclipse, IAR Embedded Workbench, and other leading IDEs. Extensive hands-on experience in building robust firmware and embedded applications, including setting up scalable build environments using Makefiles, linker scripts, and cross-compilation toolchains. Adept at driving process improvements and mentoring engineering teams on embedded technologies, tools, and workflows—resulting in enhanced team performance and code quality. Experienced in version control (Git, SVN) and CI/CD integration using Jenkins, recognized for analytical rigor, attention to detail, and effective communication skills in both individual and cross-functional team settings.

Overview

8
years of professional experience
4
years of post-secondary education
2
Languages

Work History

Landis & Gyr

Senior Firmware Engineer
03.2022 - Current

Landis & Gyr

Firmware Engineer
03.2020 - 03.2022

ITC Infotech

Associate IT consultant
07.2017 - 02.2020

Education

Uttar Pradesh Technical University

B.Tech. from Electrical and Electronics
01.2012 - 01.2016

University Overview

GPA: 65.8%

UP Board

XII from Science + Math

University Overview

GPA: 70%

UP Board

X

University Overview

GPA: 72.5%

Skills

Linux

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Extra Curricular Activities

  • Winner, Mini Project Competition organized by ICEIT ABESEC Chapter at ABES Engineering College.
  • Certified Participant, Circuit Design Competition conducted by IEEE under ECE Department, ABES.
  • Coordinator, Science Academies’ Lecture Workshop on Chemical and Environmental Sciences, ABES.
  • Volunteer, Genro’12 Inter-College Techno-Cultural Fest, ABES Engineering College.
  • Coordinator, Loophole & Ethical Hacking Workshop by KYRION Digital Securities, ABES.
  • Participant, Genero’12 Techno-Cultural Fest, ABES – awarded certificate of participation.


Disclaimer

I hereby declare that all the information provided here are true to the best of my knowledge.

Personal Information

  • Gender: Male
  • Marital Status: Married

Additional Information

My GitHub Projects:

Secure MPC Communication Framework
GitHub: github.com/gargvanshaj/secure_mpc_communication

  • Designed and implemented a secure client-server architecture over TCP/IP using Boost.Asio.
  • Developed ECDSA-based challenge-response authentication (secp256k1) with pre-provisioned keys using the Trezor Crypto library.
  • Employed SHA-256 hashing and elliptic curve operations for secure identity verification.
  • Utilized Nanopb (Protocol Buffers for C) for lightweight and efficient message serialization.
  • Structured for scalability with CMake-based cross-platform build configuration.



Timeline

Senior Firmware Engineer

Landis & Gyr
03.2022 - Current

Firmware Engineer

Landis & Gyr
03.2020 - 03.2022

Associate IT consultant

ITC Infotech
07.2017 - 02.2020

Uttar Pradesh Technical University

B.Tech. from Electrical and Electronics
01.2012 - 01.2016

UP Board

XII from Science + Math
01.2012

UP Board

X
01.2010
Vanshaj GargSr. Firmware Engineer