Vaseem Shaik
RTL Design Engineer
Bengaluru
Summary
Experienced RTL Design Engineer with over 3 years of expertise in the complete RTL design flow, including specification, architecture, and synthesis. Skilled in developing, testing, and optimizing RTL code for high-performance digital systems.
Overview
3
3
years of professional experience
6
6
years of post-secondary education
3
3
Languages
Work History
Remote Programming Application for Multiple Hardware Systems
DRDO
08.2024 - Current
- Focused on testing designs on numerous hardware units where programming each unit with JTAG was impractical.
- Developed a solution to program all units into flash memory connected to FPGAs for design flexibility during testing.
- Developed FSMs for the design blocks.
- Implemented CDC techniques to solve CDC related issues
- Solved synthesis related timing issues by writing required timing constraints .
- Used Chipscope ILA to debug hardware issues
Application for tracking targets using Radar
DRDO
05.2023 - 07.2024
- This project involved developing an FPGA-based application for radar target detection, transmitting data from the antenna to a signal processing unit to calculate the target's distance and direction.
- Understood and implemented packet structures for reliable data transmission and reception.
- Created MATLAB scripts to generate test packets for validating RTL logic.
- Designed and implemented FSM-based RTL modules that sends required paramters for signal processing.
- Developed a comprehensive test plan and executed multiple test cases for functional validation.
- Performed Synthesis related timing issues by writing timing related constraints and linting checks .
- Used Xilinx ChipScope (ILA) to debug hardware issues.
IMAGE SCALER
Lattice Semiconductor
03.2022 - 04.2023
- Enhanced customer-designed RTL for pixel scaling by modifying the architecture to support processing of two or four pixels per clock .
- Assisted the design team in testing multiple test cases and gaining a deep understanding of the RTL flow for image processing at one pixel per clock.
- Developed MATLAB scripts to generate test vectors from input images and transmitted the input image pixel data using AXI stream format .
- Developed RTL codes for Video Stream
Education
B.Tech - Electronics and Communication Engineering
National Institute of Technology Patna
PATNA 01.2017 - 01.2021
Intermediate - undefined
Sri Chaitanya Junior college
01.2015 - 01.2017
Skills
VHDL
Verilog
Lint / CDC Checks
AMBA Protocols (APB, AHB, AXI)
UART
SPI
I2C
undefinedExperience
Sr.R&D Engineer (May'24 - Present )
Logic Fruit Technologies | Bangalore .
R&D Engineer (Jan'22 - Apr'24)
Logic Fruit Technologies | Bangalore .
Timeline
Remote Programming Application for Multiple Hardware Systems
DRDO
08.2024 - Current
Application for tracking targets using Radar
DRDO
05.2023 - 07.2024
IMAGE SCALER
Lattice Semiconductor
03.2022 - 04.2023
B.Tech - Electronics and Communication Engineering
National Institute of Technology Patna
01.2017 - 01.2021
Intermediate - undefined
Sri Chaitanya Junior college
01.2015 - 01.2017
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