Vikas Reddy Gaddam

• Technical Experience: 18+ years of experience in the field of Layout design, Analog layouts design like current references, bandgap references,Sense Amplifier, Memory of single port, 2port ,multi port, dual port memories. Standard Cell Layout designs LVT,SVT,ULVT libraries . Skill coding (CAD), batch scripting, IR/EM analysis flow setup using Totem and EMIR fixing.
• Managing Experience: Managed successful three layout projects from scratch, ten layout maintenance projects delivered from LEF to GDS, and led the ten-member experienced team.

1.  RF1HD  compiler  Layout Design

July 2023 — December 2023  

Project Details: Layout design for RF1HD port memory with mux2,mux4 ,mux8,  mux16, preliminary LEF to Final GDS,as per the customer requirements,this  compiler has 1600+ Instances. Multiple Verifications apart from LVS, DRC, EMIR  on all 1600+ compilers  

Technology/Foundry: SAMSUNG 14nm.  

Tools Used: VIRTUOSO XL, Calibre (DRC/LVS/DFM verifications)  

Role: Leaf cell Design from scratch, GCNTL, LCNTL,PGCNTL for all versions.  Instance Layout design of MUX2 ,LVS clean.

2. Skill Coding to derive SVT, HVT librry from LVT library  

June 2013 — August 2013  

Project Details: Skill coding to derived  LVT,HVT lib  from LVT library  

Technology/Foundry: TSMC 28 nm.  

Tools Used: VIRTUOSO XL, Calibre (DRC/LVS/DFM verifications)  Role:  Skill code developer to derive  LVT,HVT libraries , Batch scripts to run  LVS,DRC for entire library.

3.Current References, Bandgap references Layout Design 

January 2019 — April 2019  

Project Details:  Analog Layout design of Current references, Bandgap references  

Technology/Foundry: TSMC 28nm.  

Tools Used: VIRTUOSO XL, Calibre (DRC/LVS/DFM verifications)  

Role: Leaf cell Design of OPAMP, Current Mirrors, Bandgap References , Current  references.

4. R2PV/R2PU Layout Design Using Compiler with Butterfly
architecture for Low leakage
Project Details: Layout design for 2 port memory with single bank, single control,
Single IO Layout Design from preliminary LEF to final DRC & LVS cleaning for
793 compiler macros. This project has higher poly lengths, higher poly pitches, More
LVT devices to get Low leakages, with Butterfly architecture
Technology/Foundry: 22FDSOI Global Foundry.
Tools Used: Virtuoso XL Layout Editor, Caliber, SOS, Jenkins.
Role: Leaded the Team for 10 members, guided about 22FDX technology, & Memory
architecture, Preliminary lef numbers delivery, Project Planning, resource planning,
Layout power planning, Quick layout verification (LVS & DRC) debug, guiding &
solving about SOS database issues. More importantly, drawn very highly compact
layouts.Project-9: Standard-cell Layout design.

5.  Standard-cell Layout design

Project Details: Layouts designed for Standard cells library in 28nm technology.
Technology/Foundry: TSMC cmos28nm
Tools Used: Virtuoso Layout Editor, Caliber.
Role: Owning design of layout for Inverter series, Buffer series, OR cell series, CSA
cells, at Netlogic & Smsilicon Pvt limited