Vinayak R Ganji
Memory Design Engineer
Bangalore,KA
Summary
Custom Circuit Tools and Flows Engineer with over 10 years of work experience on various types of Memory Compilers like SRAMs, Multiport Register Files, TCAM, Synthesizable RFs, ROM and eFLASH. Skilled in creating Cell and Block level Schematics and running Circuit Simulations, Critical path Modelling, Monte-Carlo analysis, RC Extraction, .LIB Characterization, Full-instance Post-layout sims and Reliability checks like Ageing, EMIR, ERC etc.
Overview
13
13
years of professional experience
Work History
Lead Engineer - Characterization
Svayam Semi
Bangalore, India
07.2026 - Current
- Spearheaded characterization flows (timing, power, noise) for SRAM memories and custom/standard cells using Cadence Liberate/LiberateMX, improving library delivery turnaround time.
- Developed comprehensive reliability flows (EMIR, Aging, Variation) using Totem, RelXpert and Solido, ensuring robust silicon sign-off and reducing electromigration risk across complex IP blocks.
Lead Design Engineer
Velaura, Previously Auradine
Bengaluru, India
10.2025 - 06.2026
- Driving timing and power characterization of standard and custom cells on advanced N3P/N3E technologies for low-power vector processing designs.
- Evaluated performance of complex arithmetic/data-path cells (multi-bit adders, compressors, multiplexers, multipliers).
- Performed statistical variation and stability analysis of flip-flops using Solido Variation Designer across PVT corners.
Member Technical Staff
GlobalFoundries
Bangalore
06.2019 - 04.2025
- Timing and Power Characterization of 12nm 6P(3R3W) RF, 3P(2R1W) RF and 22nm NTSRAM memories on full-instance post-layout RC netlist using Cadence Liberate/MX. Flow set up from scratch and executed successfully.
- Cell and block level Schematics creation and Critical path modelling using Virtuoso. Extraction flow using StarRC. Pre-layout and Post-layout simulations using HSpice and Spectre.
- High-Sigma Monte Carlo simulations and analysis on Read, Write paths and internal Timing Margins analysis using Solido Variation Designer.
- Signal and Power EMIR simulations on RC extracted netlists using Voltus-Fi, guiding layout team to address hotspots. Aging Reliability analysis run using RelXpert and circuit electrical rule checks (ERC) using Virtuoso PVS.
- Read performance Analysis of eFlash (28nm/55nm/40nm-ESF3-NOR type) through pre/post-layout simulation using PrimeSim and Spectre-XPS
- Designed and validated Digital blocks such as Read Decoder, Block Swapping and Block Erase features for 28nm ESF3 design.
- Owned block and instance level RCC extraction flow for eFlash memories using Synopsys StarRC parasitic extraction tool
- Exposure to In-Memory computing in MRAM DIMA(Deep In Memory Architecture) Compiler development. Extrapolating the single instance design to compiler friendly schematics.
Component Design Engineer
Intel Technologies India
Bangalore
07.2013 - 02.2019
- Developed and optimized EMIR flow using TOTEM and EMIR analysis on SRAM and ROM memory systems on 14nm and 10nm technology.
- Critical path modelling and Post-layout simulations of ROM using HSpice and XA.
- Timing and Power Characterization for .LIB on Intel’s internal Char and QA flow.
- 14nm 2PRF and 4PRF Signal and Power EMIR run with TOTEM, Ageing using MOSRA, LIB QA done using Intel’s internal LIB Trend check and QA flow.
- Conducted comprehensive analysis of 10nm TCAM schematics through SPICE simulations with HSPICE and XA EMIR, applying TOTEM aging techniques using MOSRA.
Education
M. TECH - VLSI and Embedded Systems
PESIT
Bangalore, KA, India01-2013
B.E. - Electronics and Communication
TCE
Gadag, KA, India03.2008
Skills
- Proficient in most of memory development flows/tools like characterization, EMIR flow, Aging and ERC
- Expertise in Cadence Liberate, LiberateMX memory characterization tools, StarRC, and Post-layout simulation
- Good understanding of Digital Design
Accomplishments
- Design and implementation a block-swapping read decoder for eFlash memory, replacing conventional serial decoding architecture while maintaining zero PPA overhead and improving resistance to data pattern extraction attacks.
- Implementation Block erase functionality in eFLASH memory with less than 1% area and power impact.
Timeline
Lead Engineer - Characterization
Svayam Semi
07.2026 - Current
Lead Design Engineer
Velaura, Previously Auradine
10.2025 - 06.2026
Member Technical Staff
GlobalFoundries
06.2019 - 04.2025
Component Design Engineer
Intel Technologies India
07.2013 - 02.2019
M. TECH - VLSI and Embedded Systems
PESIT
B.E. - Electronics and Communication
TCE