Vishnu Vandana Puvvala

Looking for an opportunity where I can apply my skills and talent which would help to develop myself and the organization. Talented Engineer with 3 years of design and Verification experience. Proficient in System Verilog, UVM, Synopsys VCS and DVE and Test bench Methodology. Versed in Protocols like APB, AHB, AXI, UART, I2S and DMA. Willing to work in rigorous environments and known for remaining composed in all types of situations.

• SV_Foundation
• UVM_Foundation
• DV_Debug
• Digital Design

I am looking forward for growing in my career and will work with full potential to achieve organizational goals and I hereby declare that the information furnished above is up to my knowledge.

COD1:

Client : INTEL(Cheeta Flow)

• Camero drive1 (COD1) is IFS's first-generation Microcontroller unit (MCU). It will be based on ARM architecture and many industry-standard third-party IPs.
• Writing the test cases for new features and producing the dumps and verifying dumps based on my specification reaches.
• Working on modification of Testbench based on new releases.
• Working on writing coverage models for some blocks and working on to achieve 100% coverage.
• Code tests from C Core to Uncore.
• Working on coverage model for DMA and writing test cases and created an HSD.
• Configuration of protocols like UART, DMA and GPIO Pin Muxing
• Creation of corresponding hex files in C.
• Received “PAT ON BACK AWARD” for showing excellence in the work.

DR ED PROTOCOL(ETHERNET)

Client : INTEL

• Creation of Example Design and do the required enhancements as per the IP requirement using TCL scripting.
• Implementation of clock frequency check for ETOC (25g with 1ge) variant check the functionality and integrate to ITF
• Implementation of wrong dynamic reconfiguration and integrate it to ITF.
• Running the Hardware tests and debug the error if it has a failure.
• Running the tests in ITF flow, Execution of Random seed Runs and Debug the failures.
• Sanity Testing for the overlay given and debug the failures.
• Stress testing and debug the failures. GUI testing for all types of variants with all parameters, Created many HSD.
• Debug for TX lanes stable issue, Tx-Rx reset issue, Packet mismatch issue.

SERIALLITE 4

Client: INTEL

Tools used: Avatar flow (2.0), Verdi, Perforce, Quartus, Spect, CRC error detection and correction using Verdi tool. 

• SQA owner for both hardware and simulation tasks.
• Analyzing and debugging SQA failures every week.
• Long hour and repetitive testing for debugging the root cause of the failure. Adding the STP signal and analyzing the failures.
• Triggering IP Hammer tasks (Simulation tasks), Adding a new feature of Analog parameters and adding them in Quartus and modifying scripts accordingly.
• Creation of Example Design and do the required enhancements as per the IP requirement using TCL scripting. Created many HSD’s as a part pf SQA debugs.

Advanced Memory Technology (AMT)

Client : INTEL

• The AMT is a next generation advanced memory technology.
• Understand the AMT Specifications.
• Creating the verification test plan as per the SPEC analysis.
• Creating the Test Bench Architecture Document., Developed Test Bench environment