Aakash Diwan
Bengaluru
Summary
Silicon Physical Design Engineer with a robust background in driving end-to-end physical design for GPU blocks, consistently exceeding PPA goals. Expertise in synthesis, STA, and timing closure across multiple chip tape-outs, ensuring timely delivery and quality. Proven ability in debugging and optimizing critical paths for high-performance designs.
Overview
9
9
years of professional experience
Work History
Silicon Physical Design Engineer
Google India
Bangalore
05.2022 - Current
- Drove end-to-end physical design for a key GPU block (8-10% of total power), outperforming on all aggressive PPA design goals
- Drove DVFS exploration and timing bottleneck analysis, redefining PPA targets across multiple SoC projects.
- Partnered to drive critical STA workflows across multiple chip tapeouts, executing timing closure, SDC constraint refinement, ECO planning, and clock tree optimization.
- Led chip bring-up activities, identifying and fixing critical path failures at top level and submodule levels.
Senior Design Engineer
Texas Instruments
Bangalore
07.2020 - 05.2022
- Owned full-chip synthesis and STA, leading to successful tape-out of mixed-signal BLE SoCs
- Developed comprehensive SDC constraints for multi-clock BLE SOCs, enhancing design accuracy and performance
- Streamlined IP synthesis flows by developing unified guidelines, facilitating cross-project adoption and reducing turnaround time
- Conducted clock divergence analysis to mitigate OCV effects on critical paths, improving quality of CTS
Associate Staff Engineer
Samsung Semiconductor India R&D
Bangalore
03.2017 - 06.2020
- Quickly up-skilled as a fresher and contributed to building the foundation of SSIR's ARM core IP hardening efforts.
- Successfully drove the Synthesis and timing closure of ARM Cortex-A53, A72, A76, and A55 cores across advanced 28FDSOI, 14LPP, and 8LPP process nodes
- Developed and fine-tuned Synthesis and PnR recipes from scratch to deliver significant PPA improvement for high performance cores
- Executed end-to-end RTL-to-GDSII implementation for ARM CPU test chips, managing the complete physical design and sign-off flow to ensure tapeout readiness
Education
M.Tech - VLSI and Microelectronics
Indian Institute of Technology, Bombay
05-2015
Other Skills And Responsibilities
- Advanced CMOS Device Physics
- Deep-Dive Analytical Debugging
- Technical Mentorship & Onboarding
Timeline
Silicon Physical Design Engineer
Google India
05.2022 - Current
Senior Design Engineer
Texas Instruments
07.2020 - 05.2022
Associate Staff Engineer
Samsung Semiconductor India R&D
03.2017 - 06.2020
M.Tech - VLSI and Microelectronics
Indian Institute of Technology, Bombay