Saurabh Kumar
Patna
Summary
Accomplished Senior Silicon Design Engineer at AMD India, specializing in SoC verification and low-power architecture design. Demonstrated analytical problem-solving skills while enhancing power management practices and authoring robust test cases in C++. Proficient in System Verilog and UVM methodologies, driving efficiency in complex projects.
Overview
4
4
years of professional experience
Work History
Senior Silicon Design Engineer
AMD India Private Limited
Hyderabad
03.2022 - Current
- Performed Server SoC verification related to Core Power management features including Core-Pstate ,Core-Cstate and PC6.
- Directed SoC level native low power (NLP) verification initiatives for enhanced efficiency.
- UPF verification for improved power management practices.
- Authored test cases leveraging C++ and Assembly language on an x86 platform for thorough testing processes.
- Acquired strong knowledge of protocols such as AXI and PCIe, maintaining high standards for coverage and checking mechanisms.
- Leveraged debugging expertise with Synopsys Verdi tools to identify and rectify issues.
- Engaged in feature bring-up on AI Chiplet, contributing to technological advancements.
- Applied Jenkins tools for regression testing while managing multiple projects concurrently.
Senior Research Fellow
IIT Goa
06.2021 - 09.2022
- Developed design automation for intelligent vision hardware in cyber-physical systems.
- Proposed low-power architecture for floating-point multiplier utilizing memorization technique.
- Implemented hardware solutions using Verilog HDL for efficient performance.
VLSI DV Engineer
L&T Technology Services
Mysore
09.2021 - 03.2022
- Gained expertise in System Verilog and UVM methodologies for IP level verification.
Education
MTech - School of Electrical Sciences
Indian Institute of Technology Goa
Goa05-2021
BE - Electronics & Telecommunication
Dr. D Y Patil Institute of Technology
Pune05-2018
Class 12th - CBSE
B.D Public School
Patna05-2014
Class 10th - CBSE
B.D Public School
Patna05-2012
Skills
- System on Chip verification
- UPF compliance testing
- Low-power architecture design strategies
- Analytical problem solving
- Debugging techniques
- Verdi and Synopsys applications
- Cadence Virtuoso tools
- C and Python coding skills
- Linux OS knowledge
- Verilog hardware description language
Accomplishments
- Cepheus'21 Technical Festival of IIT Goa, Event - Circuital Dilemma: - Honored as a special participant.
- Graduate Aptitude test in Engineering (GATE)-2019 in ECE, scored 615/1000 with AIR 1992 & 98.18 Gate Percentile.
- International Olympiad of Science achieved AIR 227.
- International Olympiad of Mathematics achieved AIR 2139.
Projects
MTech project : "VLSI implementation of polar decoders"
To reduce the bit error rate in communication systems, error correction code is widely investigated, we aim to develop reduced complexity FEC algorithms, validate a digital system, as well as implementation and verification of the same using high-performance FPGAs, designing RTL code using VHDL for implementation of polar decoding algorithm in Xilinx Vivado 2020.1 platform
Extracurriculars And Hobbies
- Attended Seminar & Conferences on VDAT 2020, 4th IEEE ITC India 2020, 2020 International conference on SPCOM.
- Participated in Circuit Fixer-1 in MindSpark'14 organized by College of Engineering, Pune.
- Attended the 'PCB designing' & 'Robotics' workshop conducted at D.R D Y Patil Institute of Technology, Pune.
- Love to travel & explore, watch motivational movies & videos.
Positions Of Responsibility
- Senior Silicon Design Engineer, owning all low-power features with respect to multichiplet SoC viewpoint
- Silicon Design Engineer 2, SOC Architecture & debugging, AMD India Pvt. Ltd.
- Teaching Assistant, EE-201: Signal and systems, Autumn Semester 2020, IIT Goa
- Teaching Assistant, EE-340: Communication Lab, Spring Semester 2020, IIT Goa
- Teaching assistant, EE-236: Electronics Devices Lab, autumn semester 2019, IIT Goa
- Zion 2016, event coordinator, SWITCH event - DYPIET, Pune Cultural Fest
Timeline
Senior Silicon Design Engineer
AMD India Private Limited
03.2022 - Current
VLSI DV Engineer
L&T Technology Services
09.2021 - 03.2022
Senior Research Fellow
IIT Goa
06.2021 - 09.2022
MTech - School of Electrical Sciences
Indian Institute of Technology Goa
BE - Electronics & Telecommunication
Dr. D Y Patil Institute of Technology
Class 12th - CBSE
B.D Public School
Class 10th - CBSE
B.D Public School