Mohit Sharma

• Drove 10+ Instruction Based Sampling(IBS), Secure Nested Paging (SNP) Security ISA features Core Level Post-silicon Verification.
• Worked on feature implementation from Testplanning to Coding Stimulus Directed tests/Constrained Random Exerciser to Coverage Closure.
• Enabled all features meeting all milestone in time based on metrics.
• Debugged and found RTL/Arch(Spec)/Tools/Testbench bugs as part of enablement.
• Overcome any major challenges as part of Enablement.

Core Verification Team(Pre-silicon):

• Worked on Instruction based sampling(IBS) ISA feature Core Level Pre-silicon Verification.
• Worked on debugging signatures and maintaining regression passrates.
• Coded/Enhanced Directed Assembly tests for IBS.
• Implemented Core Level Arch SV Assertions for IBS feature.

Core Verification Team(Post-silicon):

• Worked on Instruction based sampling(IBS) ISA feature Core Level Post-silicon Verification.
• Maintained Core Level Arch SV Assertions inline between pre-silicon & post-silicon.
• Enhanced Exerciser Stimulus to catch bugs at post silicon level.
• Reproduced post-silicon issues at pre-silicon using Directed ASM Test/Constraint Random Exerciser using Core Level Assertions.

Cache Verification Team:

• Worked on Cache/Core IP Level Gatesims.
• Worked on debugging signatures and fixing them.
• Worked on Functional Coverage Closure and Checker Corrections on similar methodology as UVM based methodology.
• Worked on Microcode debugs and coordinate with RTL/Architects in fixing them.

DFT MBIST Verification Team:

• Worked on debugging signatures and maintaining regression passrates.
• Enhanced Test Generation scripts.
• Developed new test generation scripts based on project requirements.

Project Title: Enhancement of Debug Testbench For Xtensa Processor

• Developed Perl script to compare two mismatched trace files to detect RTL bugs.
• Converted Debug Module Sequences from Verification Methodology Manual to Universal Verification Methodology using reference base sequences.
• Created compile-time flow of Xtensa Testbench.
• Understood basic flow of Debug Testbench for Xtensa Processor.