Srikanth Vanipenta

• Worked on Synthesis , Constraints and Timing Sign-off for DDRPHY Desktop Chips.
• Worked on a PNR Block from RTL to GDS , for a Server DDRPHY Project
• Worked on Scan Stitching , Timing Closure , Constraints updates and RTL team communication for the Updates.

STA sign-off for UMC/DDR controller / NOC / SMMU blocks .

• STA analysis and Timing Closure for DDR Memory Controller

• Electronic System Design Verification through System Verilog

• I Directly Joined here , after completing my Graduation
• My Current work is to Provide Control Electronics Equipments(Hardware), Software Support for The Power Electronics Team Who are working on Inverter,Buck Converter, Battery Charger In Railway Engine Equipments
• Also involving in Remote Monitoring of Locomotive Health