Mayank Tiwari

Verification Engineer with expertise in SoC and ASIC projects, demonstrating strong analytical skills and a keen ability to resolve complex problems. Known for implementing efficient solutions that significantly enhance productivity. Successfully contributed to team efforts, ensuring project goals are consistently met within set deadlines. Career aspirations include leading innovative verification initiatives that drive technological advancements.

AMD-India

As a member of CPL team my responsibility is to verify Clocks , reset scenarios, Time Stamp Counters(TSC) synchronization and Bootcode. Project-wise responsibilities are as below :-

1. Phoenix:

• Developed basic clock connectivity tests
• Coverage analysis

2. Strix

• Test cases to verify clock connectivity scenarios by checking end-to-end connectivity of IP with all the dedicated clock sources
• Verification of warm-reset sequence
• Verification of cold-reset sequence
• Functional level reset to verify IP's connectivity with the bus

3. Sarlak

• Testcases for Clk and Reset scenarios
• Testcases for verifying TSC synchronization
• Testcase to check the critical feature of warm-to-cold reset conversion

4. Medusa

• Developed skip clock initialization functionality
• Formulated clock connectivity checkers
• Formulated cold and warm reset checkers
• Formulated TSC checkers
• Enabled the CLK randomization

5. Olympic-Ridge (As a Lead)

• Ensuring end-to-end verification of CPL flow, including clocks, reset, TSC, boot code, and checkers
• Defining the verification strategy according to the architecture
• Formulating a test plan covering all verification hooks
• Mentoring and defining the team's responsibilities

SiFive-India

1. Sesame Project: Automation of Test Bench using Python scripts The responsibilities were as below,

• Development of the tb_config JSON file which collaborates and handles the information regarding other JSON Files like vip_config.
• The tb_config JSON file is then used in the parent python script where all the handles assigned in the files are linked with the vip_config JSON files which carries the information like agent class, monitor class, etc about other VIPs.
• The primary python script creates the objects for all the vip_config json files. It also create the object of other subscripts through which it creates the connection to generate the various files required in the TB.
• Every subscript is dedicated for the generation of a particular part of the TB like env, tb_top, etc.
• These all scripts are then ran sequentially via wake scripts.
• Successful integration of many VIPs such as I2C, I2S, Ethernet is been done using this

2. CHRONOS :

• Code the basic connectivity tests like register read‑write, sanity, initial value test for all the available modes
• Code functional tests and required functions to determine the data integrity while using cold reset and clock‑gating functionalities
• Code error scenario tests in order to corrupt the data and check the generation and handling of interrupt by ISR
• Generate Toggle coverage report along with the exception file

Waferspace

1. ODC[TEXAS] :

• Color Modes
• Video width ratio of video pattern
• Video patterns generated with external and internal timing
• Pattern Inversion

2. UniPro[Synopsys] :

• Testbench configuration, automation, clean‑up and regression

3. Inhouse [Waferspace] : IP verification of I2C master

• Development of TB architecture and VPlan
• Development of the UVM TB to verify the i2c_master DUT
• Code the directed tests to check all the functionalities of I2C master
• Check the code coverage

Qualified GATE 2014 with 96 percentile