Summary
Overview
Work History
Education
Skills
Personal Information
Certification
Timeline
Generic

Abhinav Choudhary

Delhi

Summary

Currently working in Synopsys as Staff Engr & have 10 years of experience in developing SRAM layouts and managing projects at various techno nodes:

  • TSMC 2nm(N2P),3nm(N3E),12/16nm
  • SAMSUNG 4nm
  • SMIC 14nm (Techno node enablement for foundry).
  • INTEL 16nm
  • HULALI 28nm, UMC 22nm .
  • Worked on FINFET/FDSOI/BULK-CMOS process nodes.
  • Have Knowledge of Layout related checks: DRC/LVS/DFM/EMIR.
  • Have knowledge of Memory development cycle from leafcell development to compiler delivery
  • Have good knowledge of memory functioning related to column muxing, Banking, Row decoding, Sense Amplifier, and memory self-timing.
  • Knows how to reduce critical signal RC and ensure the quality of SPF delivery for memory characterization.
  • Have worked upon tools like Synospys Custom Designer/XA, Cadence Virtuoso, mentor graphics calibre.
  • Have knowledge of Shell scripting, TCL, Perl. Developed various layout automation scripts and was recognized for developing the flow to enable SMIC Foundry AA style.

Overview

11
11
years of professional experience
1
1
Certification

Work History

Staff, Layout Engineer

SYNOPSYS INDIA
07.2018 - Current

Worked on various memory compilers at FinFet technology including high speed, Hight Density and Register files

Techno nodes worked upon:

  • Currently Working on TSMC N2P, Compiler Development Phase.
  • TSMC 12nm (Oct 2023-march 2024) : Compiler Scope was PDK refresh and to improve compiler Quality.
  • INTEL 16nm (22nm) (Jan 2023-October2023): Compiler scope is reduction in area and addition of dual power rail feature.
  • TSMC 3nm ( (22nm) (May 2023-Dec 2023): Scratch compiler Development.
  • SAMSUNG 4nm: (2020-2022) Compiler development from scratch and was responsible for sense amp development, compiler level LVS activity, Test chip LEF, developed automation to create chcells for RC extractions, script to put top metallization layer with proper coloring at each leaf cells with proper spacing. Other activities include: - EM/IR cleaning at compiler level, and other checks to enhance quality of IP.
  • HUALI-28nm/UMC-22nm (2017/2018): Wok was related to porting and enabling customer bitcell over the memory.
  • SMIC 12/14nm (16nm, 2016-2019): Work was related to enabling foundry at 14nm node, Developed foundry specific flow for its required AA layout style. Multiple releases were made to enhance customer's yield issue with respective time to time pdk refresh. Successfully managed one compiler and assisted other team members at that platform to make successful tapeout on time
  • TSMC 16nm (2016): Work was related to pdk refresh and a memory feature enablement.

MEMORY LAYOUT ENGINEER

ZIA SEMICONDUCTOR INDIA
01.2014 - 12.2018
  • Worked as Contractor at STMicroelectronics (2014-2015) and worked at FDSOI technology
  • Work was related to DRC/LVS/EM-IR correction/LUP/DFM checks
  • Worked as Contractor at Synopsys Noida (2016-2018)

Education

B.Tech - Electronics and Communication

Ambedkar Institute of Advanced Technical & Research Institute, Govt of Delhi (NSUT East Campus)
01.2013

Skills

  • Shell Scripting
  • TCL
  • PERL

Personal Information

  • Total Experience: 10 Years 3 Months
  • Date of Birth: 09/10/90
  • Gender: Male
  • Marital Status: Married

Certification

Circuits And Electronics 6.002x (Massachusetts

Institute Of Technology

Valid Certificate Number (edx.org)

Timeline

Staff, Layout Engineer

SYNOPSYS INDIA
07.2018 - Current

MEMORY LAYOUT ENGINEER

ZIA SEMICONDUCTOR INDIA
01.2014 - 12.2018

B.Tech - Electronics and Communication

Ambedkar Institute of Advanced Technical & Research Institute, Govt of Delhi (NSUT East Campus)
Abhinav Choudhary