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TCAM & BCAM IP :

• Worked closely with Circuit Designers and developed layout of GIO Block, GC Block, LIO slice including Sense Amplifier from standard cells to block level for TCAM and BCAM IP in 40 nm process nodes.
• Helped in IP integration and participated in continuous improvement by generating suggestions, engaging in problem-solving activities to support teamwork.

Luminous Computing Testchip :

Worked on the layout design of a Test Chip. Contributed to the layout of 15 bit Analog Comparator, Trans-Impedance Amplifier block in 7 nm process nodes.

MRAM IP :

Worked on the layout devvelopment from floorplan to EMIR check for the various Analog blocks.

Responsible for the layouts of Current Mirror, Differential Pair, Level Shifter, Opamp, Write Regulator, Ring Oscillator etc. in 28 nm FDSOI nodes.