Nikhil Singh
Noida
Summary
Hand on experience on :
- PLANAR CMOS : 90nm, 45nm, 32nm, 28nm, 22nm.
- Finfet : 22nm, 14nm, 11nm, 10nm, 7nm, 5nm, 3nm, 2nm.
Layout Methodologies :
- Quality control using customized checklist.
- Test case generation for CAD teams.
- Interacting with CAD team.
- Interfacing with CAD and Circuit Design team for various layout solution.
- ASIC layout development for Embedded SRAM,ROM and Synthesizable memory compiler with Zero delinquency and 100% quality.
- Checklist Development and Quality review process development.
- Work Flow deployment for Validation sequence.
Layout Fundamental and Validation Applied :
- Cross talk shielding, Common-Centroid matching, Interdigitated layout, WPE,STI,Jumper Antenna, Transistor VT rising,Power Gating Optimization,Gate level Latch-up,Bit-cell environment Matching.
- DRC,LVS,LVL,RC Extraction,DFM,Antenna,Density,IR ,EM.
Overview
12
12
years of professional experience
Work History
Staff Layout Engineer
ARM Embedded technologies Pvt. Ltd
Noida
01.2018 - Current
- TSMC 5nm and 2nm:
- Guidelines were followed to custom route analog IPs according to PERC guidelines.
- Demonstrated expertise in SOC level DRC, LVS, PERC and DFM as well as proficiency in Antenna and related endeavors.
- Demonstrated proficiency in using Synopsis ICV and Mentor Calibre Verification tools.
- Utilized strong understanding of Cadence Innovus tool to optimize TTCs.
- Streamlined DRC, PERC, and other physical verification issues through close collaboration with SOC PNR Engineering.
- Intel 14nm
- Conducted comprehensive QA verification for memory compiler design.
- Conducted impact and timeline analysis of PDK changes throughout the development phase.
- Ensured feasibility and seamless implementation of ECO and PDK changes, meeting customer deadlines.
- Successfully achieved all target dates for testchip and full compiler releases.
R&D Engineer I
Synopsys India
Noida
04.2012 - 01.2018
- Intel 10nm
- Developed and implemented Finfet Based Technology
- Handled the layout design of diverse memory blocks including control logic, decoders, and sense-amplifiers.
- Updated placement files and extracted RC of leaf cells. Conducted CIR updates, performed LEF checks, and generated instances.
- Achieved higher efficiency in engineering change orders by utilizing EM and IR drop DFM, density checks, and ECOs.
- Intel 14nm
- Streamlined operations and improved performance of Two port Ultra high-density Leakage Control Register File 128Kk sync Compiler with Cap-Check, Mini array Release, and area update.
- Optimized instance level DRC, LVS, ERC, array rule check and EM/IR drop fixes.
- Consistently ensured ontime delivery of test chips and released comprehensive compiler package.
- Intel 22nm
- Ensured accurate functionality of compiler area, performed cap-check tasks, and successfully launched Mini-Array releases.
- Carried out several instance level checks such as DRC, LVS, ERC, array check along with EM/IR fixes.
- Layout Top Automation
- Streamlined the automation of technology porting from previous layouts.
- Implemented automated methods for precise metal RC extraction and layout pattern identification.
- Implemented automated system to accurately place layout blocks in specified orientation and sequence.
- Enhanced efficiency by automating the drawing of global and local metals in layout.
- Streamlined the creation of Prelim LEF layout by implementing automation.
Education
Diploma - VLSI Design
C-DAC
Noida01-2012
B.Tech - Electrical, Electronics And Communications Engineering
GNIR
Greater Noida08-2010
Skills
- Layout Editor : CDesigner, Virtuso, Laker
- Layout Validation : Hercules,ICV,StarRC,HSIMRA
- Scripting Language : Linux Shell,TCL,Skill
- Operating System : Linux, Window
- Design development
- Project Planning
- Root Cause Analysis
Profile Highlights
Hand on experience on :
- PLANAR CMOS : 90nm, 45nm, 32nm, 28nm, 22nm.
- Finfet : 22nm, 14nm, 11nm, 10nm, 7nm, 5nm, 3nm, 2nm.
Layout Methodologies :
- Quality control using customized checklist.
- Test case generation for CAD teams.
- Interacting with CAD team.
- Interfacing with CAD and Circuit Design team for various layout solution.
- ASIC layout development for Embedded SRAM,ROM and Synthesizable memory compiler with Zero delinquency and 100% quality.
- Checklist Development and Quality review process development.
- Work Flow deployment for Validation sequence.
Layout Fundamental and Validation Applied :
- Cross talk shielding, Common-Centroid matching, Interdigitated layout, WPE,STI,Jumper Antenna, Transistor VT rising,Power Gating Optimization,Gate level Latch-up,Bit-cell environment Matching.
- DRC,LVS,LVL,RC Extraction,DFM,Antenna,Density,IR ,EM.
References
References available upon request.
Timeline
Staff Layout Engineer
ARM Embedded technologies Pvt. Ltd
01.2018 - Current
R&D Engineer I
Synopsys India
04.2012 - 01.2018
Diploma - VLSI Design
C-DAC
B.Tech - Electrical, Electronics And Communications Engineering
GNIR
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