Abhishek Dhasmana

Project 1: Tech Node 10 nm

• Worked on INTEL Project as Physical Design (Proper Hand on in Synthesis flow, Auto place and route flow, reduce congestion techniques, and ability to resolve basic errors).

Project 2: Tech Node 40 nm

• Owned Synthesis, Place and Route and STA.
• Collaborated closely with the frontend team to optimize the golden netlist through numerous iteration of synthesis.
• Conducted multiple iteration for resolving congression issue.
• Proper hand on in macro placement under macro guidlines, place keepout margin, Added Phyisical cells ( WELLTAP, ENDCAP cells).

• Responsible for Testing, Regression, Verification and Customer support.
• Agnisys. INC is a leading supplier of Electronic Design Automation software for solving complex design and verification problems in system development.