Naveen C

• Leading full-chip Physical Synthesis and STA activities for complex SoC designs.
• Analyzed data to support decision-making in design improvements.
• Owning top-level MCMM timing closure across all modes and corners.
• Drove setup/hold closure and reduced congestion while optimizing PPA at full-chip level for enhanced performance.
• Managed cross-block integration, resolving top-level timing violations to support design integrity.
• Performing signoff STA including OCV/AOCV, CRPR, SI/crosstalk analysis, and ECO validation.
• Defined timing closure strategies and risk mitigation plans, ensuring readiness for tapeout.
• Coordinating with RTL, DFT, PD, CAD, and signoff teams to meet milestone commitments.
• Leading backend execution, tracking project milestones, and ensuring final tapeout signoff.

Performed block-level synthesis and SDC development.

• Executed formal LEC to validate RTL against netlist and ECO, ensuring design integrity and compliance.
• Worked on SpyGlass for Logic DRCs analysis of PRE-Netlist and POST-Netlist
• Implemented UPF-based low power design including clock gating, power gating, MV domains, isolation, level shifters, and retention cells.
• Analyzed STA reports and debugged setup/hold/slew violations to achieve timing closure objectives.
• Performed pre-layout and post-layout STA with SPEF back-annotation.
• Supported top-level STA with custom timing checks and violation debugging.
• Collaborated with RTL, DFT, STA, and backend teams to facilitate timing closure and meet project milestones.

• Worked on Top-Level Synthesis and STA for full-chip integration.
• Led full-chip timing analysis and formal verification closure to ensure design integrity.
• Delivered and supported methodology flow, including WS environment enablement for PNR/PI teams.
• Handled complete RTL-to-GDSII (PNR) implementation flow.
• Performed floorplanning for high-macro designs with IR-aware power planning.
• Executed timing-driven placement, clock tree synthesis, routing, and congestion optimization, enhancing overall design performance.
• Closed setup/hold timing across MCMM scenarios.
• Resolved DRC/LVS violations and ensured clean signoff.
• Delivered high-quality GDSII that met aggressive power, performance, and area requirements for successful tapeout.

• Led block-level synthesis and drove aggressive timing and area optimization to meet PPA targets.
• Closed setup and hold timing across multiple MCM/MCMM scenarios while supporting top-level STA with custom timing checks and debugging timing violations to enhance overall timing performance.
• Managed end-to-end physical design activities, including floorplanning, power planning, macro placement, placement optimization, CTS, routing, and congestion reduction to achieve efficient layout.
• Supported top-level STA by debugging complex timing violations and closing custom timing checks.
• Applied GCA for constraint validation and detailed clock analysis to ensure timing robustness.
• Conducted Logical Equivalence Check (LEC) using Formality, systematically debugging equivalence mismatches to ensure design integrity.
• Performed signoff checks including DRC and LVS and delivered tapeout-ready GDS meeting stringent PPA targets.